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captouch programmable controller for single-electrode capacitance sensors ad7147 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2008 analog devices, inc. all rights reserved. features programmable capacitance-to-digital converter (cdc) femtofarad resolution 13 capacitance sensor inputs 9 ms update rate, all 13 sensor inputs no external rc components required automatic conversion sequencer on-chip automatic calibration logic automatic compensation for environmental changes automatic adaptive threshold and sensitivity levels register map is compatible with the ad7142 on-chip ram to store calibration data spi-compatible (serial-peripheral-interface-compatible) serial interface (ad7147) i 2 c-compatible serial interface (ad7147-1) separate v drive level for serial interface interrupt output and general- purpose input/output (gpio) 24-lead, 4 mm 4 mm lfcsp 2.6 v to 3.3 v supply voltage low operating current full power mode: 1 ma low power mode: 21.5 a applications cell phones personal music and multimedia players smart handheld devices television, a/v, and remote controls gaming consoles digital still cameras general description the ad7147 captouch? controller is designed for use with capacitance sensors implementing functions such as buttons, scroll bars, and wheels. the sensors need only one pcb layer, enabling ultrathin applications. the ad7147 is an integrated cdc with on-chip environmental calibration. the cdc has 13 inputs channeled through a switch matrix to a 16-bit, 250 khz sigma-delta (-) converter. the cdc is capable of sensing changes in the capacitance of the external sensors and uses this information to register a sensor activation. by programming the registers, the user has full control over the cdc setup. high resolution sensors require minor software to run on the host processor. functional block diagram calibration engine serial interface and control logic calibration ram power-on reset logic interrupt and gpio logic excitation source a c shield v cc gnd bias control and data registers 16-bit - cdc switch matrix 19 cin0 20 cin1 21 cin2 22 cin3 23 cin4 24 cin5 1 cin6 2 cin7 3 cin8 4 cin9 5 cin10 6 cin11 7 cin12 v drive gpio 8 11 10 9 18 12 13 14 15 16 17 sdo/ sda sdi/ add0 sclk cs/ add1 int ad7147/ ad7147-1 06663-001 figure 1. the ad7147 is designed for single electrode capacitance sensors (grounded sensors). there is an active shield output to minimize noise pickup in the sensor. the ad7147 has on-chip calibration logic to compensate for changes in the ambient environment. the calibration sequence is performed automatically and at continuous intervals as long as the sensors are not touched. this ensures that there are no false or nonregistering touches on the external sensors due to a changing environment. the ad7147 has an spi-compatible serial interface, and the ad7147-1 has an i 2 c?-compatible serial interface. both parts have an interrupt output, as well as a gpio. there is a v drive pin to set the voltage level for the serial interface independent of v cc . the ad7147 is available in a 24-lead, 4 mm 4 mm lfcsp and operates from a 2.6 v to 3.6 v supply. the operating current con- sumption in low power mode is typically 26 a for 13 sensors.
ad7147 rev. a | page 2 of 72 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? average current specifications .................................................. 4 ? spi timing specifications (ad7147) ......................................... 5 ? i 2 c timing specifications (ad7147-1) ..................................... 6 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configurations and function descriptions ........................... 8 ? typical performance characteristics ............................................. 9 ? theory of operation ...................................................................... 11 ? capacitance sensing theory ..................................................... 11 ? bias pin ....................................................................................... 12 ? operating modes ........................................................................ 12 ? capacitiance-to-digital converter ............................................... 14 ? oversampling the cdc output ............................................... 14 ? capacitance sensor offset control .......................................... 14 ? conversion sequencer ............................................................... 14 ? cdc conversion sequence time ............................................ 16 ? cdc conversion results ........................................................... 16 ? capacitance sensor input configuration .................................... 17 ? cinx input multiplexer setup .................................................. 17 ? single-ended connections to the cdc .................................. 17 ? noncontact proximity detection ................................................. 18 ? recalibration ............................................................................... 18 ? proximity sensitivity .................................................................. 18 ? ff_skip_cnt ............................................................................ 21 ? environmental calibration ........................................................... 23 ? capacitance sensor behavior without calibration ............... 23 ? threshold equations .................................................................. 24 ? capacitance sensor behavior with calibration ...................... 24 ? slow fifo .................................................................................... 24 ? slow_filter_update_lvl .............................................. 25 ? adaptive threshold and sensitivity ............................................. 26 ? interrupt output ............................................................................. 28 ? cdc conversion-complete interrupt .................................... 28 ? sensor-touch interrupt ............................................................. 28 ? gpio int output control ....................................................... 30 ? outputs ............................................................................................ 32 ? ac shield output .......................................................................... 32 ? general-purpose input/output (gpio) ................................. 32 ? using the gpio to turn on/off an led ................................ 32 ? serial interface ................................................................................ 33 ? spi interface ................................................................................ 33 ? i 2 c-compatible interface .......................................................... 35 ? v drive input ................................................................................. 37 ? pcb design guidelines ................................................................. 38 ? capacitive sensor board mechanical specifications ............. 38 ? chip scale packages ................................................................... 38 ? power-up sequence ....................................................................... 39 ? typical application circuits ......................................................... 40 ? register map ................................................................................... 41 ? detailed register descriptions ..................................................... 42 ? bank 1 registers ......................................................................... 42 ? bank 2 registers ......................................................................... 52 ? bank 3 registers ......................................................................... 57 ? outline dimensions ....................................................................... 69 ? ordering guide .......................................................................... 69 ? revision history 8/08rev. 0 to rev. a changes to table 3 ............................................................................ 4 added figure 3, renumbered sequentially .................................. 6 changes to low power mode section ......................................... 13 added latency from touch to response section ...................... 13 added low latency from touch to response section .............. 13 changes to figure 60 and figure 61 ............................................. 4 0 c hanges to figure 62 ...................................................................... 4 1 added exposed pad notation to outline dimensions ............. 6 9 9/07revision 0: initial version
ad7147 rev. a | page 3 of 72 specifications v cc = 2.6 v to 3.6 v, t a = ?40 o c to +85c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments capacitance-to-digital converter update rate 8.73 9 9.27 ms 12 conversion stages, decimation = 64 17.46 18 18.54 ms 12 conversion stages, decimation = 128 34.9 36 37.1 ms 12 conversion stages, decimation = 256 resolution 16 bits cinx input range 8 pf no missing codes 16 bits guaranteed by design, but not production tested cinx input leakage 25 na maximum output load 20 pf capacitance load on cinx to ground total unadjusted error 20 % output noise (peak-to-peak) 12 codes decimation rate = 64 7 codes decimation rate = 128 3 codes decimation rate = 256 output noise (rms) 1.1 codes decimation rate = 64 0.8 codes decimation rate = 128 0.5 codes decimation rate = 256 c stray offset range 20 pf c stray offset resolution 0.32 pf low power mode delay accuracy 4 % percentage of 200 ms, 400 ms, 600 ms, or 800 ms ac shield frequency 250 khz output voltage 0 v cc v oscillating short-circuit source current 10 ma short-circuit sink current 10 ma maximum output load 150 pf capacitance load on ac shield to ground logic inputs (sdi, sclk, cs , sda, gpio) v ih input high voltage 0.7 v drive v v il input low voltage 0.4 v i ih input high current ?1 a v in = v drive i il input low current 1 a v in = gnd hysteresis 150 mv open-drain outputs (sclk, sda, int ) v ol output low voltage 0.4 v i sink = ?1 ma i oh output high leakage current 0.1 1 a v out = v drive logic outputs (sdo, gpio) v ol output low voltage 0.4 v i sink = 1 ma, v drive = 1.65 v to 3.6 v v oh output high voltage v drive ? 0.6 v i source = 1 ma, v drive = 1.65 v to 3.6 v gpio, sdo floating state leakage current 1 a pin three-state, leakage measured to gnd and v cc power v cc 2.6 3.3 3.6 v v drive 1.65 3.6 v serial interface operating voltage i cc 0.9 1 ma in full power mode, v cc + v drive 15.5 21.5 a low power mode, converter idle, v cc + v drive , decimation = 256 2.3 7.5 a full shutdown, v cc + v drive
ad7147 rev. a | page 4 of 72 average current specifications table 2. typical average current in low power mode 1 low power decimation current values of conversion stages (a) mode delay rate 1 2 3 4 5 6 7 8 9 10 11 12 200 ms 64 20.83 24.18 27.52 30.82 34.11 37.37 40.6 43.81 46.99 50.16 53.3 56.41 128 25.3 31.92 38.45 44.87 51.21 57.45 63.6 69.66 75.63 81.52 87.33 93.05 256 34.11 46.99 59.51 71.66 83.47 94.94 106.1 116.96 127.52 137.81 147.82 157.58 400 ms 64 18.17 19.86 21.55 23.23 24.9 26.57 28.23 29.88 31.53 33.17 34.81 36.44 128 20.43 23.79 27.12 30.43 33.72 36.98 40.22 43.43 46.62 49.78 52.93 56.05 256 24.9 31.53 38.06 44.5 50.83 57.08 63.23 69.3 75.28 81.17 86.98 92.71 600 ms 64 17.28 18.41 19.54 20.67 21.79 22.91 24.03 25.14 26.25 27.36 28.47 29.57 128 18.79 21.04 23.28 25.51 27.73 29.94 32.13 34.32 36.49 38.65 40.81 42.95 256 21.79 26.25 30.67 35.04 39.37 43.66 47.9 52.11 56.27 60.39 64.47 68.51 800 ms 64 16.84 17.69 18.53 19.38 20.23 21.07 21.91 22.75 23.59 24.43 25.26 26.09 128 17.97 19.66 21.35 23.03 24.7 26.37 28.03 29.69 31.34 32.98 34.62 36.25 256 20.23 23.59 26.93 30.24 33.53 36.79 40.03 43.24 46.43 49.6 52.74 55.86 1 v cc = 3.3 v, t a = 25c, load = 50 pf. table 3. maximum average current in low power mode 1 low power decimation current values of conversion stages (a) mode delay rate 1 2 3 4 5 6 7 8 9 10 11 12 200 ms 64 27.96 32.06 36.12 40.15 44.16 48.12 52.06 55.97 59.85 63.69 67.51 71.29 128 33.41 41.49 49.44 57.26 64.97 72.55 80.02 87.37 94.61 101.74 108.77 115.69 256 44.16 59.85 75.05 89.79 104.09 117.97 131.45 144.53 157.25 169.61 181.63 193.33 400 ms 64 24.74 26.8 28.86 30.91 32.95 34.99 37.01 39.03 41.04 43.04 45.03 47.02 128 27.49 31.59 35.66 39.7 43.71 47.68 51.62 55.53 59.41 63.26 67.08 70.87 256 32.95 41.04 49 56.83 64.54 72.12 79.6 86.96 94.2 101.34 108.37 115.3 600 ms 64 23.66 25.04 26.42 27.79 29.17 30.53 31.89 33.25 34.61 35.96 37.31 38.66 128 25.5 28.25 30.99 33.71 36.41 39.1 41.78 44.44 47.09 49.72 52.34 54.95 256 29.17 34.61 40 45.33 50.6 55.82 60.98 66.09 71.15 76.15 81.1 86.01 800 ms 64 23.12 24.16 25.19 26.23 27.26 28.29 29.32 30.34 31.36 32.38 33.4 34.42 128 24.5 26.57 28.63 30.68 32.72 34.76 36.79 38.8 40.81 42.81 44.81 46.79 256 27.26 31.36 35.44 39.47 43.48 47.46 51.4 55.31 59.19 63.04 66.86 70.66 1 v cc = 3.6 v, t a = ?40c to +85c, load = 50 pf.
ad7147 rev. a | page 5 of 72 spi timing specifications (ad7147) t a = ?40c to +85c, sample tested at 25c to ensure compliance. v drive = 1.65 v to 3.6 v, and v cc = 2.6 v to 3.6 v, unless otherwise noted. all input signals are specified with t r = t f = 5 ns (10% to 90% of v cc ) and timed from a voltage level of 1.6 v. table 4. spi timing specifications parameter limit unit description f sclk 5 mhz max sclk frequency t 1 5 ns min cs falling edge to first sclk falling edge t 2 20 ns min sclk high pulse width t 3 20 ns min sclk low pulse width t 4 15 ns min sdi setup time t 5 15 ns min sdi hold time t 6 20 ns max sdo access time after sclk falling edge t 7 16 ns max cs rising edge to sdo high impedance t 8 15 ns min sclk rising edge to cs high spi timing diagram cs scl k sdi sdo t 1 11 6 15 msb lsb 23 msb lsb 12 15 16 t 2 t 4 t 5 t 3 t 6 t 7 t 8 06663-002 figure 2. spi detailed timing diagram
ad7147 rev. a | page 6 of 72 i 2 c timing specifications (ad7147-1) t a = ?40c to +85c, sample tested at 25c to ensure compliance. v drive = 1.65 v to 3.6 v, and v cc = 2.6 v to 3.6 v, unless otherwise noted. all input signals timed from a voltage level of 1.6 v. table 5. i 2 c timing specifications 1 parameter limit unit description f sclk 400 khz max t 1 0.6 s min start condition hold time, t hd; sta t 2 1.3 s min clock low period, t low t 3 0.6 s min clock high period, t high t 4 100 ns min data setup time, t su; dat t 5 300 ns min data hold time, t hd; dat t 6 0.6 s min stop condition setup time, t su; sto t 7 0.6 s min start condition setup time, t su; sta t 8 1.3 s min bus-free time between stop and start conditions, t buf t r 300 ns max clock/data rise time t f 300 ns max clock/data fall time 1 guaranteed by design, not production tested. i 2 c timing diagram sclk sda t r t f t 2 t 5 t 1 t 3 t 4 stop start stop start t 7 t 6 t 1 t 8 06663-003 figure 3. i 2 c detailed timing diagram 200a i ol 200a i oh 1.6v to output pin c l 50pf 06663-004 figure 4. load circuit for digita l output timing specifications
ad7147 rev. a | page 7 of 72 absolute maximum ratings table 6. parameter rating v cc to gnd ?0.3 v to +3.6 v analog input voltage to gnd ?0.3 v to v cc + 0.3 v digital input voltage to gnd ?0.3 v to v drive + 0.3 v digital output voltage to gnd ?0.3 v to v drive + 0.3 v input current to any pin except supplies 1 10 ma esd rating (human body model) 2.5 kv operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c lfcsp power dissipation 450 mw ja thermal impedance 135.7c/w ir reflow peak temperature 260c (0.5c) lead temperature (soldering 10 sec) 300c 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7147 rev. a | page 8 of 72 pin configurations and function descriptions pin 1 indicator 1 cin6 2 cin7 3 cin8 4 cin9 5 cin10 6 cin11 15 sclk 16 cs 17 int 18 gpio 14 sdi 13 sdo 7 cin12 8 ac shield 9 bias 11 v cc 12 v drive 10 gnd 21 cin2 22 cin3 23 cin4 24 cin5 20 cin1 19 cin0 ad7147 top view (not to scale) 06663-005 notes 1. the exposed pad is not connected internally. for increased reliability of the solder joints and maximum thermal capability it is recommended that the pad be soldered to the ground plane. figure 5. ad7147 pin configuration pin 1 indicator 1 cin6 2 cin7 3 cin8 4 cin9 5 cin10 6 cin11 15 sclk 16 add1 17 int 18 gpio 14 add0 13 sda 7 cin12 8 ac shield 9 bias 11 v cc 12 v drive 10 gnd 21 cin2 22 cin3 23 cin4 24 cin5 20 cin1 19 cin0 ad7147-1 top view (not to scale) 06663-006 notes 1. the exposed pad is not connected internally. for increased reliability of the solder joints and maximum thermal capability it is recommended that the pad be soldered to the ground plane. figure 6. ad7147-1 pin configuration table 7. pin function descriptions pin no. ad7147 ad7147-1 mnemonic description 1 1 cin6 capacitance sensor input. 2 2 cin7 capacitance sensor input. 3 3 cin8 capacitance sensor input. 4 4 cin9 capacitance sensor input. 5 5 cin10 capacitance sensor input. 6 6 cin11 capacitance sensor input. 7 7 cin12 capacitance sensor input. 8 8 ac shield cdc active shield output. connect to external shield or plane. 9 9 bias bias node for internal circuitry. requires 10 nf capacitor to ground. 10 10 gnd ground reference point for all circuitry. 11 11 v cc supply voltage. 12 12 v drive serial interface operating voltage supply. 13 n/a sdo spi serial data output. n/a 13 sda i 2 c serial data input/output. sd a requires pull-up resistor. 14 n/a sdi spi serial data input. n/a 14 add0 i 2 c address bit 0. 15 15 sclk clock input for serial interface. 16 n/a cs spi chip select signal. n/a 16 add1 i 2 c address bit 1. 17 17 int general-purpose open-drain interrupt output. programmable polarity; requires pull-up resistor. 18 18 gpio programmable gpio. 19 19 cin0 capacitance sensor input. 20 20 cin1 capacitance sensor input. 21 21 cin2 capacitance sensor input. 22 22 cin3 capacitance sensor input. 23 23 cin4 capacitance sensor input. 24 24 cin5 capacitance sensor input.
ad7147 rev. a | page 9 of 72 typical performance characteristics 935 795 2.6 3.7 06663-007 v cc (v) i cc (a) 915 895 875 855 835 815 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 decimation = 256 decimation = 128 decimation = 64 figure 7. supply current vs. supply voltage 180 0 2.5 3.7 06663-061 v cc (v) i cc ( a) 160 140 120 100 80 60 40 20 200ms 400ms 600ms 800ms 2.7 2.9 3.1 3.3 3.5 figure 8. low power supply current vs. supply voltage, decimation rate = 256 0.12 0 2.5 3.7 06663-009 v cc (v) i cc (ma) 0.10 0.08 0.06 0.04 0.02 400ms 800ms 600ms 200ms 2.72.93.13.33.5 figure 9. low power supply current vs. supply voltage, decimation rate = 128 70 0 06663-060 v cc (v) i cc ( a) 60 50 40 30 20 10 600ms 800ms 200ms 400ms 2.5 3.7 2.7 2.9 3.1 3.3 3.5 figure 10. low power supply current vs. supply voltage, decimation rate = 64 2.5 0 2.7 06663-010 v cc (v) i cc (a) 2.0 1.5 1.0 0.5 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 figure 11. shutdown supply current vs. supply voltage 1150 900 0 06663-062 ac shield capacitive load (pf) i cc (a) 1100 1050 1000 950 100 200 300 400 500 figure 12. supply current vs. capacitive load on ac shield
ad7147 rev. a | page 10 of 72 58000 40000 0 06663-063 ac shield capacitive load (pf) cdc code (d) 100 200 300 400 500 56000 54000 52000 50000 48000 46000 44000 42000 figure 13. output code vs . capacitive load on ac shield 960 780 ?60 ?40 ?20 0 20 40 60 80 100 120 06663-013 temperature (c) i cc (a) 940 920 900 880 860 840 820 800 3.3v 3.6v 2.6v figure 14. supply current vs. temperature 12 0 ?45 135 06663-014 temperature (c) i cc (a) 10 8 6 4 2 ?25?51535557595115 3.6v 2.6v 3.3v figure 15. shutdown suppl y current vs. temperature 160 0 25 50 100 200 400 800 1600 3200 6400 12800 25600 51200 102400 204800 409600 819200 1640000 06663-064 sine wave frequency (hz) cdc noise p-p (lsb) 140 120 100 80 60 40 20 25mv 75mv 125mv 175mv 50mv 100mv 150mv 200mv figure 16. power supply sine wave rejection, v cc = 3.6 v 120 0 25 50 100 200 400 800 1600 3200 6400 12800 25600 51200 102400 204800 409600 819200 1640000 06663-065 square wave frequency (hz) cdc noise p-p (lsb) 25mv 75mv 125mv 175mv 50mv 100mv 150mv 200mv 100 80 60 40 20 figure 17. power supply square wave rejection, v cc = 3.6 v 35 0 0 10000 20000 30000 40000 50000 60000 06663-016 cdc output code input capacitance (pf) 30 25 20 15 10 5 figure 18. cdc linearity, v cc = 3.3 v
ad7147 rev. a | page 11 of 72 theory of operation the ad7147 and ad7147-1 are cdcs with on-chip environ- mental compensation. they are intended for use in portable systems requiring high resolution user input. the internal circuitry consists of a 16-bit, - converter that can change a capacitive input signal into a digital value. there are 13 input pins, cin0 to cin12, on the ad7147 or ad7147-1. a switch matrix routes the input signals to the cdc. the result of each capacitance-to-digital conversion is stored in on-chip registers. the host subsequently reads the results over the serial interface. the ad7147 has an spi interface, and the ad7147-1 has an i 2 c interface, ensuring that the parts are compatible with a wide range of host processors. ad7147 refers to both the ad7147 and ad7147-1, unless otherwise noted, from this point forward in this data sheet. the ad7147 interfaces with up to 13 external capacitance sensors. these sensors can be arranged as buttons, scroll bars, or wheels, or as a combination of sensor types. the external sensors consist of an electrode on a single- or multiple-layer pcb that interfaces directly to the ad7147. the ad7147 can be set up to implement any set of input sensors by programming the on-chip registers. the registers can also be programmed to control features such as averaging, offsets, and gains for each of the external sensors. there is an on-chip sequencer that controls how each of the capacitance inputs is polled. the ad7147 has on-chip digital logic and 528 words of ram that are used for environmental compensation. the effects of humidity, temperature, and other environmental factors can affect the operation of capacitance sensors. transparent to the user, the ad7147 performs continuous calibration to compen- sate for these effects, allowing the ad7147 to consistently provide error-free results. the ad7147 requires a companion algorithm that runs on the host or another microcontroller to implement high resolution sensor functions, such as scroll bars or wheels. however, no companion algorithm is required to implement buttons. button sensors are implemented on chip, entirely in digital logic. the ad7147 can be programmed to operate in either full power mode or low power automatic wake-up mode. the automatic wake-up mode is particularly suited for portable devices that require low power operation to provide the user with significant power savings and full functionality. the ad7147 has an interrupt output, int , to indicate when new data has been placed into the registers. int is used to interrupt the host on sensor activation. the ad7147 operates from a 2.6 v to 3.6 v supply and is available in a 24-lead, 4 mm 4 mm lfcsp. capacitance sensing theory the ad7147 measures capacitance changes from single electrode sensors. the sensor electrode on the pcb comprises one plate of a virtual capacitor. the other plate of the capacitor is the users finger, which is grounded with respect to the sensor input. the ad7147 first outputs an excitation signal to charge the plate of the capacitor. when the user comes close to the sensor, the virtual capacitor is formed, with the user acting as the second capacitor plate. plastic cover ad7147 sensor pcb mux - adc 16-bit data excitation signal 250khz 06663-017 figure 19. capacitance-sensing method a square wave excitation signal is applied to cinx during the conversion, and the modulator continuously samples the charge going through cinx. the output of the modulator is processed via a digital filter, and the resulting digital data is stored in the cdc_result_sx registers for each conversion stage, at address 0x00b to address 0x016.
ad7147 rev. a | page 12 of 72 registering a sensor activation when a user approaches a sensor, the total capacitance associated with that sensor changes and is measured by the ad7147. if the change causes a set threshold to be exceeded, the ad7147 interprets this as a sensor activation. on-chip threshold limits are used to determine when a sensor activation occurs. figure 20 shows the change in cdc_result_sx when a user activates a sensor. the sensor is deemed to be active only when the value of cdc_result_sx is either greater than the value of stagex_high_threshold or less than the value of stagex_low_threshold. cdc output codes stagex_high_threshold stagex_low_threshold sensor active (a) sensor active (b) cdc_result_sx ambient or no-touch value 06663-018 figure 20. sensor activation thresholds in figure 20 , two sensor activations are shown. sensor active a occurs when a sensor is connected to the positive input of the converter. in this case, when a user activates the sensor, there is an increase in cdc code, and the value of cdc_result_sx exceeds that of stagex_high_threshold. sensor active b occurs when the sensor is connected to the negative input of the converter. in this case, when a user activates the sensor, there is a decrease in cdc code, and the value of cdc_result_sx becomes less than the value of stagex_low_threshold. for each conversion stage, the stagex_high_threshold and stagex_low_threshold registers are in register bank 3. the values in these registers are updated automatically by the ad7147 due to its environmental calibration and adaptive threshold logic. at power-up, the values in the stagex_high_threshold and stagex_low_threshold registers are the same as those in the stagex_offset_high and stagex_offset_low registers in bank 2. the user must program the stagex_offset _high and stagex_offset_low registers on device power- up. see the environmental calibration section of the data sheet for more information. complete solution for capacitance sensing analog devices, inc., provides a complete solution for capacitance sensing. the two main elements to the solution are the sensor pcb and the ad7147. if the application requires high resolution sensors such as scroll bars or wheels, software is required that runs on the host processor. the memory requirements for the host depend on the sensor and are typically 10 kb of code and 600 bytes of data memory, depending on the sensor type. ad7147 sensor pcb spi or i 2 c host processor 1 mips 10kb rom 600 bytes ram 06663-019 figure 21. three-part capacitance sensing solution analog devices supplies the sensor pcb footprint design libraries to the customer and supplies any necessary software on an open source basis. bias pin this pin is connected internally to a bias node of the ad7147. to ensure correct operation of the ad7147, connect a 10 nf capacitor between the bias pin and ground. the voltage seen at the bias pin is v cc /2. operating modes the ad7147 has three operating modes. full power mode, where the device is always fully powered, is suited for applications where power is not a concern (for example, game consoles that have an ac power supply). low power mode, where the part automatically powers down when no sensor is active, is tailored to provide significant power savings compared with full power mode and is suited for mobile applications, where power must be conserved. in shutdown mode, the part shuts down completely. the power_mode bits (bit 0 and bit 1) of the control register set the operating mode on the ad7147. the control register is at address 0x000. table 8 shows the power_mode settings for each operating mode. to put the ad7147 into shutdown mode, set the power_mode bits to either 01 or 11. table 8. power_mode settings power_mode bits operating mode 00 full power mode 01 shutdown mode 10 low power mode 11 shutdown mode the power-on default setting of the power_mode bits is 00, full power mode.
ad7147 rev. a | page 13 of 72 full power mode in full power mode, all sections of the ad7147 remain fully powered and converting at all times. while a sensor is being touched, the ad7147 processes the sensor data. if no sensor is touched, the ad7147 measures the ambient capacitance level and uses this data for the on-chip compensation routines. in full power mode, the ad7147 converts at a constant rate. see the cdc conversion sequence time section for more information. low power mode when ad7147 is in low power mode, the power_mode bits are set to 10 upon device initialization. if the external sensors are not touched, the ad7147 reduces its conversion frequency, thereby greatly reducing its power consumption. the part remains in a reduced power state while the sensors are not touched. the ad7147 performs a conversion after a delay defined by the lp_conv_delay bits, and it uses this data to update the compensation logic and check if the sensors are active. the lp_conv_delay bits set the delay between conversions to 200 ms, 400 ms, 600 ms, or 800 ms. in low power mode, the total current consumption of the ad7147 is an average of the current used during a conversion and the current used while the ad7147 is waiting for the next conversion to begin. for example, when lp_conv_delay is 400 ms, the ad7147 typically uses 0.85 ma of current for 36 ms and 14 a of current for 400 ms during the conversion interval. (note that these conversion timings can be altered through the register settings. see the cdc conversion sequence time section for more information.) the time for the ad7147 to transition from a full power state to a reduced power state after the user stops touching the external sensors is configurable. the pwr_down_timeout bits (in the ambient compensation control 0 (amb_comp_ctrl0) register at address 0x002) control the time delay before the ad7147 transitions to the reduced power state after the user stops touching the sensors. latency from touch to response in low power mode, the ad7147 remains in a low power state until any one of the external sensors are touched. when a sensor is touched, the ad7147 begins a conversion sequence every 36 ms to read back data from the sensors. this means that the latency between the user touching the sensor, and the ad7147 responding, is a maximum of lp_conv_delay ms. low latency from to uch to response in low power mode, the ad7147p model remains in a low power state until proximity is detected on any one of the external sensors. when proximity is detected, the ad714p begins a conversion sequence every 36 ms, or 18 ms, or 9 ms to readback data from the sensors. the latency between first touch and the ad7147p responding is much reduced, compared to the ad7147, because the part is already in a full power state by the time the user has touched the sensor. no yes yes no timeout ad7147p setup and initialization power_mode = 10 user in proximity to sensor? conversion sequence every lp_conv_delay update compensation logic data path proximity timer countdown conversion sequence every 9/18/36ms for sensor readback user in proximity to sensor? 06663-066 no yes yes no timeout ad7147 setup and initialization power_mode = 10 any sensor touched? conversion sequence every lp_conv_delay update compensation logic data path proximity timer countdown conversion sequence every 9/18/36ms for sensor readback any sensor touched? 06663-020 figure 23. low power mode operation, ad7147p figure 22. low power mode operation, ad7147
ad7147 rev. a | page 14 of 72 capacitiance-to-digital converter the capacitance-to-digital converter on the ad7147 has a - architecture with 16-bit resolution. there are 13 possible inputs to the cdc that are connected to the input of the converter through a switch matrix. the sampling frequency of the cdc is 250 khz. oversampling the cdc output the decimation rate, or oversampling ratio, is determined by bits[9:8] of the power control (pwr_control) register (address 0x000), as listed in table 9 . table 9. cdc decimation rate decimation bits decimation rate cdc output rate per stage (ms) 00 256 3.072 01 128 1.536 10 64 0.768 11 64 0.768 the decimation process on the ad7147 is an averaging process, where a number of samples are taken and the averaged result is output. due to the architecture of the digital filter employed, the number of samples taken (per stage) is equal to 3 the decimation rate. so 3 256 or 3 128 samples are averaged to obtain each stage result. the decimation process reduces the amount of noise present in the final cdc result. however, the higher the decimation rate, the lower the output rate per stage; therefore, there is a trade-off possible between the amount of noise in the signal and the speed of sampling. capacitance sensor offset control there are two programmable dacs on board the ad7147 to null the effect of any stray capacitances on the cdc measurement. these offsets are due to stray capacitance to ground. a s implified block diagram in figure 24 shows how to apply the stagex_afe_offset registers to null the offsets. the 6-bit pos_afe_offset and neg_afe_offset bits program the offset dac to provide 0.32 pf resolution offset adjustment over a range of 20 pf. th e best practice is to ensure that the cdc output for any stage is approximately equal to midscale (~32,700) when all sensors are inactive. to correctly offset the stray capacitance to ground for each stage, use the following procedure: 1. read back the cdc value from the cdc_result_sx register. 2. if this value is not close to midscale, increase the value of pos_afe_offset or neg_afe_offset (depending on if the cinx input is connected to the positive or negative input of the converter) by 1. the cinx connections are determined by the stagex_connection registers. 3. if the cdc value in cdc_result_sx is now closer to midscale, repeat step 2. if the cdc value is further from midscale, decrease the pos_afe_offset or neg_afe_offset value by 1. the goal is to ensure that the cdc_result_sx is as close to midscale as possible. this process is only required once during the initial capacitance sensor characterization. pos_afe_offset 16-bit cdc neg_afe_offset +dac (20pf range) pos_afe_offset_swap bit neg_afe_offset_swap bit 6 6 16 cinx + _ cinx_connection_setup ?dac (20pf range) 06663-021 figure 24. analog front-end offset control conversion sequencer the ad7147 has an on-chip sequencer to implement conversion control for the input channels. up to 12 conversion stages can be performed in one sequence. each of the 12 conversions stages can measure the input from a different sensor. by using the bank 2 registers, each stage can be uniquely configured to support multiple capacitance sensor interface requirements. for example, a slider sensor can be assigned to stage1 through stage8, with a button sensor assigned to stage0. for each conversion stage, the input mux that connects the cinx inputs to the converter can have a unique setting. the ad7147 on-chip sequence controller provides conversion control, beginning with stage0. figure 25 shows a block diagram of the cdc conversion stages and cinx inputs. a conversion sequence is defined as a sequence of cdc conversions starting at stage0 and ending at the stage determined by the value programmed in the sequence_stage_num bits. depending on the number and type of capacitance sensors that are used, not all conversion stages are required. use the sequence_stage_num bits to set the number of conversions in one sequence. this number depends on the sensor interface requirements. for example, the register should be set to 5 if the cinx inputs are mapped to only six conversion stages. in addition, the stage_cal_en register should be set according to the number of stages that are used. the number of required conversion stages depends solely on the number of sensors attached to the ad7147. figure 26 shows how many conversion stages are required for each sensor and how many inputs to the ad7147 each sensor requires.
ad7147 rev. a | page 15 of 72 a button sensor generally requires one sequencer stage; this is shown in figure 26 as b1. however, it is possible to configure two button sensors to operate differentially for one conversion stage. only one button can be activated at a time; pressing both buttons simultaneously results in neither button being activated. the configuration with two button sensors operating differentially requires one conversion stage and is shown in figure 26 , with b2 and b3 representing the differentially configured button sensors. a wheel sensor requires eight stages, whereas a slider requires two stages. the result from each stage is used by the host software to determine the users position on the slider or wheel. the algorithms that perform this process are available from analog devices and are free of charge, but require signing a software license. stage11 stage10 stage9 stage8 stage7 stage6 stage5 stage4 stage3 stage2 stage1 stage0 switch matrix - 16-bit adc cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 cin8 cin9 cin10 cin11 cin12 c o n v e r s i o n s e q u e n c e 06663-022 figure 25. cdc conversion stages cdc stage0 + ? stage1 + ? cdc ad7147 sequencer cdc stage2 + ? stage3 + ? cdc cdc stage4 + ? stage5 + ? cdc cdc stage6 + ? stage7 + ? cdc scroll wheel buttons stage8 cdc + ? stage9 cdc + ? ad7147 sequencer b1 b2 b3 stage10 cdc + ? stage11 cdc + ? ad7147 sequencer slider 06663-023 figure 26. sequencer setup for sensors
ad7147 rev. a | page 16 of 72 cdc conversion sequence time table 10. cdc conversion times for full power mode conversion time (ms) sequence_stage_num decimation = 64 decimation = 128 decimation = 256 0 0.768 1.536 3.072 1 1.536 3.072 6.144 2 2.304 4.608 9.216 3 3.072 6.144 12.288 4 3.84 7.68 15.36 5 4.608 9.216 18.432 6 5.376 10.752 21.504 7 6.144 12.288 24.576 8 6.912 13.824 27.648 9 7.68 15.36 30.72 10 8.448 16.896 33.792 11 9.216 18.432 36.864 the time required for the cdc to complete the measurement of all 12 stages is defined as the cd c conversion sequence time. the sequence_stage_num and decimation bits determine the conversion time, as listed in table 10 . for example, if the device is operated with a decimation rate of 128 and the sequence_stage_num bit is set to 5 for the conversion of six stages in a sequence, the conversion sequence time is 9.216 ms. full power mode cdc conversion sequence time the full power mode cdc conversion sequence time for all 12 stages is set by configuring the sequence_stage_num and decimation bits as outlined in table 10 . figure 27 shows a simplified timing diagram of the full power mode cdc conversion time. the full power mode cdc con- version time (t conv_fp ) is set using the values shown in tabl e 10 . conversion sequence n conversion sequence n + 1 conversion sequence n + 2 cdc c onversion t conv_fp 0 6663-024 figure 27. full power mode cdc conversion sequence time low power mode cdc conversion sequence time with delay the frequency of each cdc conversion while operating in the low power automatic wake-up mode is controlled by using the lp_conv_delay bits located at address 0x000[3:2] in addition to the registers listed in table 10 . this feature provides some flexibility for optimizing the tradeoff between the conversion time needed to meet system requirements and the power consumption of the ad7147. for example, maximum power savings is achieved when the lp_conv_delay bits are set to 11. with a setting of 11, the ad7147 automatically wakes up, performing a conversion every 800 ms. table 11. lp_conv_delay settings lp_conv_delay bits delay between conversions (ms) 00 200 01 400 10 600 11 800 figure 28 shows a simplified timing example of the low power mode cdc conversion time. as shown, the low power mode cdc conversion time is set by t conv_fp and the lp_conv_delay bits. conversion sequence n conversion sequence n + 1 cdc conversion lp_conv_delay t conv_lp t conv_fp 0 6663-025 figure 28. low power mode cdc conversion sequence time cdc conversion results certain high resolution sensors require the host to read back the cdc conversion results for processing. the registers required for host processing are located in the bank 3 registers. the host processes the data read back from these registers using a software algorithm in order to determine position information. in addition to the results registers in the bank 3 registers, the ad7147 provides the 16-bit cdc output data directly, starting at address 0x00b of bank 1. reading back the cdc 16-bit conversion data register allows for customer-specific application data processing.
ad7147 rev. a | page 17 of 72 capacitance sensor input configuration each input connection from the external capacitance sensors to the converter of the ad7147 can be uniquely configured by using the registers in bank 2 (see table 38 ). these registers are used to configure the input pin connection setups, sensor offsets, sensor sensitivities, and sensor limits for each stage. each sensor can be individually optimized. for example, a button sensor connected to stage0 can have different sensitivity and offset values than a button with another function that is connected to a different stage. cinx input multiplexer setup table 34 and table 35 list the available options for the cinx_connection_setup bits when the sensor input pins are connected to the cdc. the ad7147 has an on-chip multiplexer that routes the input signals from each cinx pin to the input of the converter. each input pin can be tied to either the negative or positive input of the cdc, or it can be left floating. each input can also be internally connected to the bias signal to help prevent cross coupling. if an input is not used, always connect it to the bias. connecting a cinx input pin to the positive cdc input results in an increase in cdc output code when the corresponding sensor is activated. connecting a cinx input pin to the negative cdc input results in a decrease in cdc output code when the corresponding sensor is activated. the ad7147 performs a sequence of 12 conversions. the multi- plexer can have different settings for each of the 12 conversions. for example, cin0 is connected to the negative cdc input for conversion stage1, left floating for conversion stage1, and so on, for all 12 conversion stages. for each cinx input for each conversion stage, two bits control how the input is connected to the converter, as shown in figure 29 . examples to connect cin3 to the positive cdc input on stage 0 use the following setting: stage0_connection[6:0] = 0xffbf stage0_connection[12:7] = 0x2fff to connect cin0 to the positive cdc input and cin12 to the negative cin input on stage 5 use the following settings: stage5_connection[6:0] = 0xfffe stage5_connection[12:7] = 0x37ff s ingle-ended connections to the cdc a single-ended connection to the cdc is defined as one cinx input connected to either the positive or negative cdc input for one conversion stage. a differential connection to the cdc is defined as one cinx input connected to the positive cdc input and a second cinx input connected to the negative input of the cdc for one conversion stage. f or any stage, if a single-ended connection to the cdc is made in that stage, the se_connection_setup bits (bits[13:12] in the stagex_connection[12:7] register) should be applied as follows: ? se_connection_setup = 00: do not use. ? se_connection_setup = 01: single-ended connection. for this stage, there is one cinx connected to the positive cdc input. ? se_connection_setup = 10: single-ended connection. for this stage, there is one cinx connected to the negative cdc input. ? se_connection_setup = 11: differential connection. for this stage, there is one cinx connected to the nega tive cdc input and one cinx connected to the positive cdc input. these bits ensure that during a single-ended connection to the cdc, the input paths to both cdc terminals are matched, which in turn improves the power-supply rejection of the converter measurement. these bits should be applied in addition to setting the other bits in the stagex_connection registers, as outlined in the cinx input multiplexer setup section. if more than one cinx input is connected to either the positive or negative input of the converter for the same conversion, set se_connection_setup to 11. for example, if cin0 and cin3 are connected to the positive input of the cdc, set se_connection_setup to 11. cin connection setup bits cin setting 00 cinx floating 01 cinx connected to negative cdc input 10 cinx connected to positive cdc input 11 cinx connected to bias cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 cin8 cin9 cin10 cin11 cin12 + ? cdc 06663-026 figure 29. input mux configuration options
ad7147 rev. a | page 18 of 72 noncontact proximity detection the ad7147 internal signal processing continuously monitors all capacitance sensors for noncontact proximity detection. this feature provides the ability to detect when a user is approaching a sensor, at which time all internal calibration is immediately disabled while the ad7147 is automatically configured to detect a valid contact. the proximity control register bits are described in table 12 . the fp_proximity_cnt and lp_proximity_cnt register bits control the length of the calibration disable period after the user stops touching the sensor and is not in close proximity to the sensor during full or low power mode. the calibration is disabled during this period and then enabled again. figure 30 and figure 31 show examples of how these registers are used to set the calibration disable periods for the full and low power modes. the calibration disable period in full power mode is the value of the fp_proximity_cnt multiplied by 16 multiplied by the time for one conversion sequence in full power mode. the calibration disable period in low power mode is the value of the lp_proximity_cnt multiplied by 4 multiplied by the time for one conversion sequence in low power mode. recalibration in certain situations (for example, when a user hovers over a sensor for a long time), the proximity flag can be set for a long period. the environmental calibration on the ad7147 is sus- pended while proximity is detected, but changes may occur to the ambient capacitance level during the proximity event. this means that the ambient value stored on the ad7147 no longer represents the actual ambient value. in this case, even when the user is not in close proximity to the sensor, the prox- imity flag may still be set. this situation can occur if the user interaction creates some moisture on the sensor, causing the new sensor ambient value to be different from the expected value. in this situation, the ad7147 automatically forces a recalibration internally. this ensures that the ambient values are recalibrated, regardless of how long the user hovers over the sensor. a recalibration ensures maximum ad7147 sensor performance. the ad7147 recalibrates automatically when the measured cdc value exceeds the stored ambient value by an amount determined by the proximity_recal_lvl bits for a set period of time known as the recalibration timeout. in full power mode, the recali- bration timeout is controlled by fp_proximity_recal; in low power mode, by lp_proxmty_recal. the recalibration timeout in full power mode is the value of the fp_proximity_recal multiplied by the time for one conversion sequence in full power mode. the recalibration time- out in low power mode is the value of the lp_proximity_ recal multiplied by the time for one conversion sequence in low power mode. figure 32 and figure 33 show examples of how the fp_proximity_recal and lp_proximity_recal register bits control the timeout period before a recalibration while operating in the full and low power modes. in these examples, a user approaches a sensor and then leaves, but the proximity detection remains active. the measured cdc value exceeds the stored ambient value by the amount set in the proximity_recal_lvl bits for the entire timeout period. the sensor is automatically recalibrated at the end of the timeout period. proximity sensitivity the fast filter in figure 34 is used to detect when someone is close to the sensor (proximity). two conditions, detected by compa- rator 1 and comparator 2, set the internal proximity detection signal: comparator 1 detects when a user is approaching or leaving a sensor, and comparator 2 detects when a user hovers over a sensor or approaches a sensor very slowly. the sensitivity of comparator 1 is controlled by the proximity_detection_rate bits. for example, if proximity_detection_rate is set to 4, the proximity 1 signal is set when the absolute difference between word1 and word3 exceeds (4 16) lsb codes. the proximity_recal_lvl bits (address 0x003) control the sensitivity of comparator 2. for example, if proximity_ recal_lvl is set to 75, the proximity 2 signal is set when the absolute difference between the fast filter average value and the ambient value exceeds (75 16) lsb codes.
ad7147 rev. a | page 19 of 72 table 12. proximity control registers (see figure 34 ) bit name length (bits) register address description fp_proximity_cnt 4 0x002[7:4] calibrat ion disable time in full power mode. lp_proximity_cnt 4 0x002[11:8] calibration disable time in low power mode. fp_proximity_recal 8 0x004[9:0] full power mode proximity recalibration time. lp_proximity_recal 6 0x004[15:10] low power mode proximity recalibration time. proximity_recal_lvl 8 0x003[7:0] proximity recalibration level. this value multiplied by 16 controls the sensitivity of comparator 2 (see figure 34 ). proximity_detection_rate 6 0x003[13:8] proximity detection rate. this value multiplied by 16 controls the sensitivity of comparator 1 (see figure 34 ). calibration enabled calibration disabled proximity detection (internal) calibration (internal) 12345678910111213141516 cdc conversion sequence (internal) user leaves sensor area user approaches sensor 17 18 19 20 21 22 23 24 t conv_fp t caldis 06663-027 figure 30. example of full power mode proximity detection (fp_proximity_cnt = 1) notes 1. sequence conversion time t conv_lp = t conv_fp + lp_conv_delay. 2. proximity is set when user approaches the sensor, at which time the internal calibration is disabled. 3. t caldis = ( t conv_lp lp_proximity_cnt 4). calibration enabled calibration disabled proximity detection (internal) calibration (internal) t caldis t conv_lp 12345678910111213141516 cdc conversion sequence (internal) user leaves sensor area user approaches sensor 17 18 19 20 21 22 23 24 06663-028 figure 31. example of low power mode proximity detection (lp_proximity_cnt = 4)
ad7147 rev. a | page 20 of 72 calibration enabled t recal_timeout 16 30 70 t conv_fp measured cdc value > stored ambient by proximity_recal _lvl recalibration timeout proximity detection (internal) calibration (internal) cdc conversion sequence (internal) recalibration counter (internal) user approaches sensor user leaves sensor area t caldis t recal calibration disabled notes 1. sequence conversion time t conv_fp (see table 10). 2. t caldis = t conv_fp fp_proximity_cnt 16. 3. t recal_timeout = t conv_fp fp_proximity_recal. 4. t recal = 2 t conv_fp . 06663-029 figure 32. example of full power mode proximity detection with forced recalibration (fp_proximity_cnt = 1 and fp_proximity_reca l = 40) calibration enabled t recal_timeout 16 30 70 t conv_lp measured cdc value > stored ambient by proximity_recal _lvl recalibration timeout proximity detection (internal) calibration (internal) cdc conversion sequence (internal) recalibration (internal) user approaches sensor user leaves sensor area t caldis t recal calibration disabled notes 1. sequence conversion time t conv_lp = t conv_fp + lp_conv_delay. 2. t caldis = t conv_lp lp_proximity_cnt 4. 3. t recal_timeout = t conv_lp lp_proximity_recal. 4. t recal = 2 t conv_lp . 06663-030 figure 33. example of low power mode proximity detection with forced recalibration (lp_proximity_cnt = 4 and lp_proximity_recal = 40)
ad7147 rev. a | page 21 of 72 ff_skip_cnt the proximity detection fast fifo is used by the on-chip logic to determine if proximity is detected. the fast fifo expects to receive samples from the converter at a set rate. ff_skip_cnt is used to normalize the frequency of the samples going into the fifo, regardless of how many conversion stages are in a sequence. in register 0x002, bits[3:0] are the fast filter skip control, ff_skip_cnt. this value determines which cdc samples are not used (skipped) by the proximity detection fast fifo. determining the ff_skip_cnt value is required only once during the initial setup of the capacitance sensor interface. table 13 shows how ff_skip_cnt controls the update rate of the fast fifo. the recommended value for the setting when using all 12 conversion stages on the ad7147 is 0000, or no samples skipped. table 13. ff_skip_cnt settings ff_skip _cnt fast fifo update rate decimation = 64 decimation = 128 decimation = 256 0 0.768 (sequence_stage_num + 1) ms 1.536 (sequence_stage_num + 1) ms 3.072 (sequence_stage_num + 1) ms 1 1.536 (sequence_stage_num + 1) ms 3.072 (sequence_stage_num + 1) ms 6.144 (sequence_stage_num + 1) ms 2 2.3 (sequence_stage_num + 1) ms 4.608 (sequence_stage_num + 1) ms 9.216 (sequence_stage_num + 1) ms 3 3.072 (sequence_stage_num + 1) ms 6.144 (sequence_stage_num + 1) ms 12.288 (sequence_stage_num + 1) ms 4 3.84 (sequence_stage_num + 1) ms 7.68 (sequence_stage_num + 1) ms 15.36 (sequence_stage_num + 1) ms 5 4.6 (sequence_stage_num + 1) ms 9.216 (sequence_stage_num + 1) ms 18.432 (sequence_stage_num + 1) ms 6 5.376 (sequence_stage_num + 1) ms 10.752 (sequence_stage_num + 1) ms 21.504 (sequence_stage_num + 1) ms 7 6.144 (sequence_stage_num + 1) ms 12.288 (sequence_stage_num + 1) ms 24.576 (sequence_stage_num + 1) ms 8 6.912 (sequence_stage_num + 1) ms 13.824 (sequence_stage_num + 1) ms 27.648 (sequence_stage_num + 1) ms 9 7.68 (sequence_stage_num + 1) ms 15.36 (sequence_stage_num + 1) ms 30.72 (sequence_stage_num + 1) ms 10 8.448 (sequence_stage_num + 1) ms 16.896 (sequence_stage_num + 1) ms 33.792 (sequence_stage_num + 1) ms 11 9.216 (sequence_stage_num + 1) ms 18.432 (sequence_stage_num + 1) ms 36.864 (sequence_stage_num + 1) ms 12 9.984 (sequence_stage_num + 1) ms 19.968 (sequence_stage_num + 1) ms 39.936 (sequence_stage_num + 1) ms 13 10.752 (sequence_stage_num + 1) ms 21.504 (sequence_stage_num + 1) ms 43.008 (sequence_stage_num + 1) ms 14 11.52 (sequence_stage_num + 1) ms 23.04 (sequence_stage_num + 1) ms 46.08 (sequence_stage_num + 1) ms 15 12.288 (sequence_stage_num + 1) ms 24.576 (sequence_stage_num + 1) ms 49.152 (sequence_stage_num + 1) ms
ad7147 rev. a | page 22 of 72 notes 1. slow_filter_en, which is the name of the output of comparator 3, is set and sw1 is closed when |stagex_sf_ word0 ? cdc value | exceeds the value programmed in the slow_filter_update_lvl register providing proximity is not set. 2. proximity 1 is set when |stagex_ff_ word0 ? stagex_ff_word3 | exceeds the value programmed in the proximity_detection_rate register. 3. proximity 2 is set when | average ? ambient | exceeds the value programmed in the proximity_recal_lvl register. 4. description of comparator functions: comparator 1: used to detect when a user is approaching or leaving a sensor. comparator 2: used to detect when a user is hovering over a sensor or approaching a sensor very slowly. also used to detect if the sensor ambient level has changed as a result of the user interaction. for example, humidity or dirt left behind on sensor. comparator 3: used to enable the slow filter update rate. the slow filter is updated when slow_filter_en is set and proximity is not set. bank 3 registers bank 3 registers sw1 proximity slow_filter_en stagex_sf_word0 stagex_sf_word1 stagex_sf_word2 stagex_sf_word3 stagex_sf_word4 stagex_sf_word5 stagex_sf_word6 stagex_sf_word7 stagex_ff_word0 stagex_ff_word1 stagex_ff_word2 stagex_ff_word3 stagex_ff_word4 stagex_ff_word5 stagex_ff_word6 stagex_ff_word7 8 7 word(n) n = 0 comparator 3 word0 ? cdc value slow_filter_update_lvl register 0x003 stagex_sf_ambient bank 3 registers 16 cdc comparator 1 |word0 ? word3| proximity_detection_rate register 0x003 comparator 2 |average ? ambient| proximity 2 proximity_recal_lvl register 0x003 proximity 1 proximity lp_proximity_cnt register 0x002 fp_proximity_cnt register 0x002 lp_proximity_recal register 0x004 fp_proximity_recal register 0x004 proximity timing control logic cdc output code t ambient value stagex_sf_wordx stagex_ff_wordx sensor contact 06663-031 stagex_ff_avg bank 3 registers figure 34. ad7147 proximity-detection logic
ad7147 rev. a | page 23 of 72 environmental calibration cdc output codes t stagex_low_threshold stagex_high_threshold cdc ambient value changing environmental conditions sensor 1 int asserted sensor 2 int asserted 06663-032 the ad7147 provides on-chip capacitance sensor calibration to automatically adjust for environmental conditions that have an effect on the ambient levels of the capacitance sensor. the output levels of the capacitance sensor are sensitive to temperature, humidity, and, in some cases, dirt. the ad7147 achieves optimal and reliable sensor performance by continuously monitoring the cdc ambient levels and compen- sating for any environmental changes by adjusting the values of the stagex_high_threshold register and the stagex_ low_threshold registers as described in the threshold equations section. the cdc ambient level is defined as the output level of the capacitance sensor during periods when the user is not approaching or in contact with the sensor. figure 35. ideal sensor behavior with a constant ambient level capacitance sensor behavior without calibration after the ad7147 is configured, the compensation logic runs automatically with each conv ersion when the ad7147 is not being touched. this allows the ad7147 to compensate for rapidly changing environmental conditions. figure 36 shows the typical behavior of a capacitance sensor when calibration is not applied. this figure shows ambient levels drifting over time as environmental conditions change. as a result of the initial threshold levels remaining constant while the ambient levels drift upward, sensor 2 fails to detect a user contact in this example. the ambient compensation control registers provide the host with access to general setup and controls for the compensation algorithm. on-chip ram stores the compensation data for each conversion stage, as well as setup information specific for each stage. the capacitance sensor behavior with calibration section describes how the ad7147 adaptive calibration algorithm prevents such errors from occurring. figure 35 shows an example of the ideal behavior of a capaci- tance sensor, where the cdc ambient level remains constant regardless of the environmental conditions. the cdc output shown is for a pair of differential button sensors, where one sensor caused an increase and the other caused a decrease in measured capacitance when activated. the positive and negative sensor threshold levels are calculated as a percentage of the stagex_offset_high and stagex_offset_low values and are based on the threshold sensitivity settings and the ambient value. these values are sufficient to detect a sensor contact and result in the ad7147 asserting the int output when the threshold levels are exceeded. cdc output codes t cdc ambient value drifting changing environmental conditions stagex_high_threshold stagex_low_threshold sensor 1 int asserted sensor 2 int not asserted 06663-033 figure 36. typical sensor behavior without calibration
ad7147 rev. a | page 24 of 72 threshold equations on-chip logic stage high threshold y sensitivit threshold pos high offset stagex high offset stagex high offset stagex ambient sf stagex threshold high stagex _ _ 16 4 __ __ 4 __ __ __ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? + = (1) on-chip logic stage low threshold y sensitivit threshold neg low offset stagex low offset stagex low offset stagex ambient sf stagex threshold low stagex _ _ 16 4 __ __ 4 __ __ __ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? + = (2) capacitance sensor behavior with calibration the ad7147 on-chip adaptive calibration algorithm prevents sensor detection errors such as the one shown in figure 36 . this is achieved by monitoring the cdc ambient levels and readjusting the initial stagex_offset_high and stagex_offset_low values according to the amount of ambient drift measured on each sensor. based on the new stage offset values, the internal stagex_high_threshold and stagex_low_threshold values described in equation 1 and equation 2 are automatically updated. this closed-loop routine ensures the reliability and repeatable operation of every sensor connected to the ad7147 when they are subjected to dynamic environmental conditions. figure 37 shows a simplified example of how the ad7147 applies the adaptive calibration process, resulting in no interrupt errors even with changing cdc ambient levels due to dynamic environmental conditions. cdc output codes t sensor 1 int asserted 1 2 3 4 5 6 stagex_high_threshold (postcalibrated register value) changing environmental conditions 1 initial stagex_offset_high register value. 2 postcalibrated register stagex_high_threshold. 3 postcalibrated register stagex_high_threshold. 4 initial stagex_low_threshold. 5 postcalibrated register stagex_low_threshold. 6 postcalibrated register stagex_low_threshold. cdc ambient value drifting stagex_low_threshold (postcalibrated register value) sensor 2 int asserted 06663-034 figure 37. typical sensor behavior with calibration applied on the data path slow fifo a s shown in figure 34 , there are a number of fifos implemented on the ad7147. these fifos are located in bank 3 of the on-chip memory. the slow fifos are used by the on-chip logic to monitor the ambient capacitance level from each sensor. a vg_fp_skip and avg_lp_skip in register 0x001, bits[13:12] are the slow fifo skip control for full power mode, avg_fp_skip. bits[15:14] in the same register are the slow fifo skip control for low power mode, avg_lp_skip, and determine which cdc samples are not used (skipped) in the slow fifo. changing the values of the avg_fp_skip and avg_lp_skip bits slows down or speeds up the rate at which the ambient capacitance value tracks the measured capacitance value read by the converter: ? slow fifo update rate in full power mode = avg_fp_skip [(3 decimation rate) (sequence_stage_num + 1) (ff_skip_cnt + 1) 4 10 ?7 ]. ? slow fifo update rate in low power mode = (avg_lp_skip + 1) [(3 decimation rate) (sequence_stage_num + 1) (ff_skip_cnt + 1) 4 x 10 ?7 ]/[(ff_skip_cnt + 1) + lp_conv_delay]. t he slow fifo is used by the on-chip logic to track the ambient capacitance value. the slow fifo expects to receive samples from the converter at a rate between 33 ms and 40 ms. avg_fp_skip and avg_lp_skip are used to normalize the frequency of the samples going into the fifo, regardless of how many conversion stages are in a sequence. determining the avg_fp_skip and avg_lp_skip values is required only once during the initial setup of the capacitance sensor interface. the recommended values for these settings when using all 12 conversion stages on the ad7147 are as follows: ? avg_fp_skip = 00 = skip three samples ? avg_lp_skip = 00 = skip zero samples
ad7147 rev. a | page 25 of 72 slow_filter_update_lvl the slow_filter_update_lvl controls whether the most recent cdc measurement goes into the slow fifo (slow filter). the slow filter is updated when the difference between the current cdc value and the last value of the slow fifo is greater than the value of slow_filter_update_lvl. this variable is in ambient control register 1 (amb_comp_ctrl1) (address 0x003).
ad7147 rev. a | page 26 of 72 adaptive threshold and sensitivity the ad7147 provides an on-chip, self-adjusting adaptive threshold and sensitivity algorithm. this algorithm continu- ously monitors the output levels of each sensor and automatically rescales the threshold levels in proportion to the sensor area covered by the user. as a result, the ad7147 maintains optimal threshold and sensitivity levels for all users regardless of their finger sizes. the threshold level is always referenced from the ambient level and is defined as the cdc converter output level that must be exceeded before a valid sensor contact can occur. the sensitivity level is defined as how sensitive the sensor must be before a valid contact can be registered. figure 38 provides an example of how the adaptive threshold and sensitivity algorithm works. the positive and negative sensor threshold levels are calculated as a percentage of the stagex_offset_high and stagex_offset_low values and are based on the threshold sensitivity settings and the ambient value. after the ad7147 is configured, initial estimates are supplied for both stagex_offset_high and stagex_offset_low, and then the calibration engine automatically adjusts the stagex_high_threshold and stagex_low_threshold values for sensor response. the ad7147 tracks the average maximum and minimum values measured from each sensor. these values provide an indication of how the user is interacting with the sensor. a large finger results in a large average maximum or minimum value, whereas a small finger results in smaller values. when the average maximum or minimum value changes, the threshold levels are rescaled to ensure that the threshold levels are appropriate for the current user. figure 39 shows how the minimum and maximum sensor responses are tracked by the on-chip logic. reference a in figure 38 shows a less sensitive threshold level for a user with small fingers and demonstrates the disadvantages of a fixed threshold level. by enabling the adaptive threshold and sensitivity algorithm, the positive and negative threshold levels are determined by the pos_threshold_sensitivity and neg_threshold_ sensitivity bit values and by the most recent average maxi- mum sensor output value. these bits can be used to select 16 different positive and negative sensitivity levels ranging between 25% and 95.32% of the most recent average maximum output level referenced from the ambient value. the smaller the sensitivity percentage setting, the easier it is to trigger a sensor activation. reference b shows that the positive adaptive threshold level is set at almost mid-sensitivity with a 62.51% threshold level by setting pos_threshold_ sensitivity = 1000. figure 38 also provides a similar example for the negative threshold level, with neg_threshold_sensitivity = 0011. ambient level cdc output codes average maximum value stagex_offset_high 25% 95.32% 62.51% = pos_ threshold _sensitivity 25% 62.51% = pos_ threshold _sensitivity 95.32% neg_threshold_sensitivity = 39.08% 25% 95.32% 25% 95.32% sensor contacted by small finger a verage maximum value stagex_offset_low neg_threshold_sensitivity = 39.08% sensor contacted by large finger stagex_offset_high is updated stagex_offset_high is updated stagex_offset_low is updated stagex_offset_low is updated a b 0 6663-035 figure 38. example of threshold sensitivity (pos_threshold_sensitivity = 1000, neg_threshold_sensitivity = 0011)
ad7147 rev. a | page 27 of 72 bank 3 registers stagex_max_word0 stagex_max_word1 stagex_max_word2 stagex_max_word3 stagex_min_word0 stagex_min_word1 stagex_min_word2 stagex_min_word3 stagex_max_avg bank 3 registers stagex_max_temp bank 3 registers stagex_high_threshold bank 3 registers stagex_min_avg bank 3 registers stagex_min_temp bank 3 registers stagex_low_threshold bank 3 registers bank 3 registers maximum level detection logic minimum level detection logic 16 - 16-bit cdc 06663-036 figure 39. tracking the minimum and maximum average sensor values table 14. additional information about environmental calibration and adaptive threshold registers register location description register/bit neg_threshold_sensitivity bank 2 used in equati on 2. this value is programmed once at startup. neg_peak_detect bank 2 used by intern al adaptive threshold logic only. the neg_peak_detect is set to a percentage of the difference between the ambient cdc value and the minimum average cdc value. if the output of the cdc approaches the neg_peak_detect percentage of the minimum average, the minimum average value is updated. pos_threshold_sensitivity bank 2 used in equati on 1. this value is programmed once at startup. pos_peak_detect bank 2 used by internal adaptive threshold logic only. the pos_peak_detect is set to a percentage of the difference between the ambient cdc value and the maximum average cdc value. if the output of the cdc approaches the pos_peak_detect percentage of the maximum average, the maximum average value is updated. stagex_offset_low bank 2 used in equati on 2. an initial value (based on se nsor characterization) is programmed into this register at startup. the ad 7147 on-chip calibration algori thm automatically updates this register based on the amount of sensor drif t due to changing ambient conditions. set this register to 80% of the stagex_offset_low_clamp value. stagex_offset_high bank 2 used in equati on 1. an initial value (based on se nsor characterization) is programmed into this register at startup. the ad 7147 on-chip calibration algori thm automatically updates this register based on the amount of sensor drif t due to changing ambient conditions. set this register to 80% of the stagex_offset_high_clamp value. stagex_offset_high_clamp bank 2 used by internal environmen tal calibration and adaptive threshold algorithms only. an initial value (based on sensor characterization) is programmed into this register at startup. the value in this register prevents a user from causing the output value of a sensor to exceed the expected nominal value. set this register to the maximum expected sensor response or the maximum change in cdc output code. stagex_offset_low_clamp bank 2 used by internal environmen tal calibration and adaptive threshold algorithms only. an initial value (based on sensor characterization) is programmed into this register at startup. the value in this register prevents a user from causing the output value of a sensor to exceed the expected nominal value. set this register to the minimum expected sens or response or the minimum change in cdc output code. stagex_sf_ambient bank 3 used in equation 1 and equation 2. this is the ambient sensor output when the sensor is not touched, as calculated using the slow fifo. stagex_high_threshold bank 3 equation 1 value. stagex_low_threshold bank 3 equation 2 value.
ad7147 rev. a | page 28 of 72 interrupt output sensor-touch interrupt the ad7147 has an interrupt output that triggers an interrupt service routine on the host processor. the int signal is on pin 17 and is an open-drain output. there are three types of interrupt events on the ad7147: a cdc conversion-complete interrupt, a sensor touch interrupt, and a gpio interrupt. each interrupt has enable and status registers. the conversion- complete and sensor-touch (sensor-activation) interrupts can be enabled on a per-conversion-stage basis. the status registers indicate what type of interrupt triggered the int pin. status registers are cleared, and the int signal is reset high during a read operation. the signal returns high as soon as the read address has been set up. the sensor-touch interrupt mode is implemented when the host processor requires an interrupt only when a sensor is contacted. configuring the ad7147 into this mode results in the interrupt being asserted when the user makes contact with the sensor and again when the user stops touching the sensor. the second interrupt is required to alert the host processor that the user is no longer contacting the sensor. the registers located at address 0x005 and address 0x006 are used to enable the interrupt output for each stage. the registers located at address 0x008 and address 0x009 are used to read back the interrupt status for each stage. cdc conversion-complete interrupt figure 40 shows the interrupt output timing during contact with one of the sensors connected to stage0 while operating in the sensor-touch interrupt mode. for a low limit configuration, the interrupt output is asserted as soon as the sensor is contacted and again after the user has stopped contacting the sensor. (note that the interrupt output remains low until the host processor reads back the interrupt status registers located at address 0x008 and address 0x009.) the ad7147 interrupt signal asserts low to indicate the completion of a conversion stage and that new conversion result data is available in the registers. the interrupt can be independently enabled for each conversion stage. each conversion-stage-complete interrupt can be enabled via the stagex_complete_int_enable register (address 0x007). this register has a bit that corresponds to each conversion stage. setting this bit to 1 enables the interrupt for that stage. clearing this bit to 0 disables the conversion-complete interrupt for that stage. the interrupt output is asserted when there is a change in the interrupt status bits. this can indicate that a user is touching the sensor(s) for the first time, the number of sensors being touched has changed, or the user is no longer touching the sensor(s). reading the status bits in the interrupt status register shows the current sensor activations. the ad7147 interrupt should be enabled only for the last stage in a conversion sequence. for example, if there are five conver- sion stages, only the conversion-complete interrupt for stage4 is enabled. therefore, int only asserts when all five conversion stages are complete and the host can read new data from all five result registers. the interrupt is cleared by reading the stagex_ complete_int_status register located at address 0x00a. 4 2 conversion stage serial readback int output 3 1 stage1 stage0 finger on sensor finger off sensor 1 user touching sensor. 2 address 0x008 is read back to clear interrupt. 3 user stops touching sensor. 4 address 0x008 is read back to clear interrupt. 06663-037 register 0x00a is the conversion-complete interrupt status register. each bit in this register corresponds to a conversion stage. if a bit is set, it means that the conversion-complete interrupt for the corresponding stage was triggered. this register is cleared upon a read if the underlying condition that triggered the interrupt is not present. figure 40. example of sensor-touch interrupt
ad7147 rev. a | page 29 of 72 stage0 stage1 stage2 stage3 stage4 stage5 stage6 stage7 stage8 stage9 stage10 stage11 23 1 int conversions serial reads notes this is an example of a cdc conversion-complete interrupt. this timing example shows that the interrupt output has been enabled to be asserted at the end of a conversion cycle for stage0, stage5, and stage9. the interrupts for all other stages have been disabled. stagex configuration programming notes for stage0, stage5, and stage9 (x = 0, 5, 9): stagex_low_int_enable (address 0x005) = 0 stagex_high_int_enable (address 0x006) = 0 stagex_complete_int_enable (address 0x007) = 1 stagex configuration programming notes for stage1 through stage8, stage10, and stage11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11): stagex_low_int_enable (address 0x005) = 0 stagex_high_int_enable (address 0x006) = 0 stagex_complete_int_enable (address 0x007) = 0 serial readback requirements for stage0, stage5, and stage9 (this readback operation is required to clear the interrupt output. ): 1 read the stage0_complete_int_status (address 0x00a) bit 2 read the stage5_complete_int_status (address 0x00a) bit 3 read the stage9_complete_int_status (address 0x00a) bit 06663-038 figure 41. example of configuring the regist ers for conversion-complete interrupt setup 42 1 int conversions serial reads notes this is an example of a sensor-touch interrupt for a case where the low threshold levels were exceeded. for example, the sensor connected to stage0 and stage9 were contacted, and the low threshold levels were exceeded, resulting in the interrupt being asserted. the stage6 interrupt was not asserted because the user did not contact the sensor connected to stage6. stagex configuration programming notes for stage0, stage6, and stage9 (x = 0, 6, 9): stagex_low_int_enable (address 0x005) = 1 stagex_high_int_enable (address 0x006) = 0 stagex_complete_int_enable (address 0x007) = 0 stagex configuration programming notes for stage1 through stage7, stage8, stage10, and stage11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11): stagex_low_int_enable (address 0x005) = 0 stagex_high_int_enable (address 0x006) = 0 stagex_complete_int_enable (address 0x007) = 0 serial readback requirements for stage0 and stage9 (this readback operation is required to clear the interrupt output.): 1 read the stage0_low_int_status (address 0x008) bit 2 read the stage5_low_int_status (address 0x008) bit stage0 stage1 stage2 stage3 stage4 stage5 stage6 stage7 stage8 stage9 stage10 stage11 06663-039 figure 42. example of configuring the re gisters for sensor-touch interrupt setup
ad7147 rev. a | page 30 of 72 gpio int output control the int output signal can be controlled by the gpio pin when the gpio is configured as an input. the gpio is con-figured as an input by setting the gpio_setup bits in the interrupt con- figuration register to 01. see the general-purpose input/output (gpio) section for more information on configuring the gpio. enable the gpio interrupt by setting the gpio_int_enable bit in register 0x007 to 1, or disable the gpio interrupt by clearing this bit to 0. the gpio status bit in the conversion- complete interrupt status register reflects the status of the gpio interrupt. this bit is set to 1 when the gpio has triggered int . the bit is cleared upon reading the gpio_int_status bit if the condition that caused the interrupt is no longer present. the gpio interrupt can be set to trigger on a rising edge, falling edge, high level, or low level at the gpio input pin. table 15 shows how the settings of the gpio_input_config bits in the inter- rupt enable (stage_low_int_enable) register affect the behavior of int . figure 43 to figure 46 show how the interrupt output is cleared upon a read from the gpio_int_status bit. gpio input int output serial readback gpio input int output 1 1 read gpio_int_status bit to reset int output. g pio input high when register is read back gpio input low when register is read back 06663-040 figure 43. example of int output controlled by the gpio input (gp io_setup = 01, gpio_input_config = 00) gpio input int output serial readback gpio input int output 1 1 read gpio_int_status bit to reset int output. g pio input high when register is read back gpio input low when register is read back 06663-041 figure 44. example of int output controlled by the gpio input (gpio_setup = 01, gpio_input_config = 01)
ad7147 rev. a | page 31 of 72 gpio input gpio input 1 gpio input low when register is read back gpio input high when register is read back 1 read gpio_int_status bit to reset int output. int output int output serial readback 06663-042 figure 45. example of int output controlled by the gpio input (gpio_setup = 01, gpio_input_config = 10) gpio input serial readback gpio input 1 gpio input low when register is read back gpio input high when register is read back notes 1 read gpio_int_status bit to reset int output. int output int output 06663-043 figure 46. example of int output controlled by the gpio input (gpio_setup = 01, gpio_input_config = 11) table 15. gpio interrupt behavior gpio_input_config gpio pin gpio_int_status int int behavior 00 = negative level triggered 1 0 1 not triggered 00 = negative level triggered 0 1 0 asserted while signal on gpio pin is low 01 = positive edge triggered 1 1 0 pulses low at low-to-high gpio transition 01 = positive edge triggered 0 0 1 not triggered 10 = negative edge triggered 1 0 1 pulses low at high-to-low gpio transition 10 = negative edge triggered 0 1 0 not triggered 11 = positive level triggered 1 1 0 asserted while signal on gpio pin is high 11 = positive level triggered 0 0 1 not triggered
ad7147 rev. a | page 32 of 72 outputs ac shield output the ad7147 measures capacitance between cinx and ground. any capacitance to ground on the signal path between the cinx pins and the sensor is included in the ad7147 conversion result. to eliminate stray capacitance to ground, the ac shield signal should be used to shield the connection between the sensor and cinx, as shown in figure 47 . the plane around the sensors should also be connected to ac shield . cin0 cin1 cin2 cin3 ac shield ad7147 sensor pcb gnd 06663-044 figure 47. ac shield the ac shield output is the same signal waveform as the excitation signal on cinx. therefore, there is no ac current between cinx and ac shield , and any capacitance between these pins does not affect the cinx charge transfer. using ac shield eliminates capacitance-to-ground pickup, which means that the ad7147 can be placed up to 10 cm away from the sensors. this allows the ad7147 to be placed on a separate pcb than that of the sensors if the connections between the sensors and the cinx inputs are correctly shielded using ac shield . general-purpose input/output (gpio) the ad7147 has one gpio pin. it can be configured as an input or an output. the gpio_setup bits[13:12] in the interrupt enable register determine how the gpio pin is configured. table 16. gpio_setup bits gpio_setup gpio configuration 00 gpio disabled 01 input 10 output low 11 output high when the gpio is configured as an output, the voltage level on the pin is set to either a low level or a high level, as defined by the gpio_setup bits (see table 16 ). the gpio_input_config bits in the interrupt enable register determine the response of the ad7147 to a signal on the gpio pin when the gpio is configured as an input. the gpio can be configured as either active high or active low, as well as either edge triggered or level triggered (see table 17 ). table 17. gpio_input_config bits gpio_input_config gpio configuration 00 triggered on negative level (active low) 01 triggered on positive edge (active high) 10 triggered on negative edge (active low) 11 triggered on positive level (active high) when gpio is configured as an input, it triggers the interrupt output on the ad7147. table 15 lists the interrupt output behavior for each of the gpio configuration setups. using the gpio to tu rn on/off an led the gpio on the ad7147 can be used to turn on and off an led by setting the gpio as either output high or low. setting the gpio output high turns on the led; setting the gpio output low turns off the led. the gpio pin connects to a transistor that provides the drive current for the led. suitable transistors include the ktc3875 from korea electronics co., ltd. (kec). ad7147 gpio v cc ktc3875 or similar 06663-045 figure 48. controlling an led using the gpio
ad7147 rev. a | page 33 of 72 serial interface the ad7147 is available with an spi-compatible interface. the ad7147-1 is available with an i 2 c-compatible interface. both parts are the same, with the exception of the serial interface. spi interface the ad7147 has a 4-wire serial peripheral interface (spi). the spi has a data input pin (sdi) for inputting data to the device, a data output pin (sdo) for reading data back from the device, and a data clock pin (sclk) for clocking data into and out of the device. a chip select pin ( cs ) enables or disables the serial interface. cs is required for correct operation of the spi. data is clocked out of the ad7147 on the negative edge of sclk and data is clocked into the device on the positive edge of sclk. spi command word all data transactions on the spi bus begin with the master taking cs from high to low and sending out the command word. this indicates to the ad7147 whether the transaction is a read or a write and provides the address of the register from which to begin the data transfer. the following bit map shows the spi command word. msb lsb 15 14 13 12 11 10 9:0 1 1 1 0 0 r/ w register address bits[15:11] of the command word must be set to 11100 to successfully begin a bus transaction. bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a write. bits[9:0] contain the target register address. when reading or writing to more than one register, this address indicates the address of the first register to be written to or read from. writing data data is written to the ad7147 in 16-bit words. the first word written to the device is the command word, with the read/write bit set to 0. the master then supplies the 16-bit input data-word on the sdi line. the ad7147 clocks the data into the register addressed in the command word. if there is more than one word of data to be clocked in, the ad7147 automatically incre- ments the address pointer and clocks the subsequent data-word into the next register. the ad7147 continues to clock in data on the sdi line until either the master finishes the write transition by pulling cs high or the address pointer reaches its maximum value. the ad7147 address pointer does not wrap around. when it reaches its maximum value, any data provided by the master on the sdi line is ignored by the ad7147. cw 11 cw 10 cw 13 cw 12 sdi cw 15 cw 14 cw 9 cw 7 cw 6 cw 5 cw 4 cw 3 cw 2 cw 1 cw 0 d2 d1 d0 cw 8 t 1 t 4 16-bit data 5 32 6 7 8 9 10 11 12 13 14 15 16 30 31 t 8 t 5 sclk 1234 d15 d14 d13 17 18 19 cs enable word r/w register address t 2 t 3 notes 1. sdi bits are latched on sclk rising edges. sclk can idle high or low between write operations. 2. all 32 bits must be written: 16 bits for the control word and 16 bits for the data. 3. 16-bit command word settings for serial write operation: cw [15:11] = 11100 (enable word) cw [10] = 0 (r/w) cw [9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (10-bit msb-justified register address) 16-bit command word 06663-046 figure 49. single register write spi timing
ad7147 rev. a | page 34 of 72 sdi cw 15 cw 14 cw 13 cw 8 cw 1 cw 0 d15 d14 sclk cw 12 notes 1. multiple sequential registers can be loaded continuously. 2. the first (lowest address) register address is written, followed by multiple 16-bit data-words. 3. the address automatically increments with each 16-bit data-word (all 16 bits must be written). 4. cs is held low until the last desired register has been loaded. 5. 16-bit command word settings for sequential write operation: cw [15:11] = 11100 (enable word) cw [10] = 0 (r/w) cw [9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (starting msb-justified register address) d1 d0 d1 d0 d15 data for starting register address data for next register address d15 d14 1 32 234 15 16 17 18 31 3433 4847 49 cs cw 11 cw 10 cw 9 cw 7 cw 2 cw 6 cw 5 cw 4 cw 3 11 12 13 14 5678 910 enable word r/w starting register address 16-bit command word 06663-047 figure 50. sequential register write spi timing cw 11 cw 10 cw 13 cw 12 sdi cw 15 cw 14 cw 9 cw 7 cw 6 cw 5 cw 4 cw 3 cw 2 cw 1 cw 0 xxx cw 8 t 1 t 4 16-bit readback data 5 32 6 7 8 9 10 11 12 13 14 15 16 30 31 t 8 t 5 sclk 1234 xxx 17 18 19 cs xxx xxx xxx xxx sdo xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx d2 d1 d0 xxx d15 d14 d13 t 6 t 7 xxx enable word r/w register address t 2 t 3 16-bit command word notes 1. sdi bits are latched on sclk rising edges. sclk can idle high or low between write operations. 2. the 16-bit control word must be written on sdi: 5 bits for enable word, 1 bit for r/w, and 10 bits for register address. 3. the register data is read back on the sdo pin. 4. x denotes don?t care. 5. xxx denotes high impedance three-state output. 6. cs is held low until all register bits have been read back. 7. 16-bit command word settings for single readback operation: cw [15:11] = 11100 (enable word) cw [10] = 1 (r/w) cw [9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (10-bit msb-justified register address) 06663-048 figure 51. single regist er readback spi timing reading data a read transaction begins when the master writes the command word to the ad7147 with the read/write bit set to 1. the master then supplies 16 clock pulses per data-word to be read, and the ad7147 clocks out data from the addressed register on the sdo line. the first data-word is clocked out on the first falling edge of sclk following the command word, as shown in figure 51 . the ad7147 continues to clock out data on the sdo line if the master continues to supply the clock signal on sclk. the read transaction finishes when the master takes cs high. if the ad7147 address pointer reaches its maximum value, the ad7147 repeatedly clocks out data from the addressed register. the address pointer does not wrap around.
ad7147 rev. a | page 35 of 72 sdi cw 15 cw 14 cw 13 cw 8 cw 1 cw 0 xx sclk cw 12 xx xx x readback data for starting register address x x 1 32 234 15161718 31 34 33 4847 49 cw 11 cw 10 cw 9 cw 7 cw 2 cw 6 cw 5 cw 4 cw 3 11 12 13 14 5678 910 xxx xxx xxx xxx d15 d14 d1 d0 d1 d0 d15 d15 d14 xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx sdo enable word r/w register address notes 1. multiple registers can be read back continuously. 2. the 16-bit control word must be written on sdi: 5 bits for enable word, 1 bit for r/w, and 10 bits for register address. 3. the address automatically increments with each 16-bit data-word being read back on the sdo pin. 4. cs is held low until all register bits have been read back. 5. x denotes don?t care. 6. xxx denotes high impedance three-state output. 7. 16-bit command word settings for sequential readback operation: cw [15:11] = 11100 (enable word) cw [10] = 1 (r/w) cw [9:0] = [ad9, ad8, ad7, ad6, ad5, ad4, ad3, ad2, ad1, ad0] (starting msb-justified register address) readback data for next register address cs 16-bit command word 06663-049 figure 52. sequential register readback spi timing i 2 c-compatible interface the ad7147-1 supports the industry standard 2-wire i 2 c serial interface protocol. the two wires associated with the i 2 c timing are the sclk and sda inputs. the sda is an i/o pin that allows both register write and register readback operations. the ad7147-1 is always a slave device on the i 2 c serial interface bus. it has a 7-bit device address, address 0101 1xx. the lower two bits are set by tying the add0 and add1 pins high or low. the ad7147-1 responds when the master device sends its device address over the bus. the ad7147-1 cannot initiate data trans- fers on the bus. table 18. ad7147-1 i 2 c device address add1 add0 i 2 c address 0 0 0101 100 0 1 0101 101 1 0 0101 110 1 1 0101 111 data transfer data is transferred over the i 2 c serial interface in 8-bit bytes. the master initiates a data transfer by establishing a start con- dition, defined as a high-to-low transition on the serial data line, sda, while the serial clock line, sclk, remains high. this indicates that an address/data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit that determines the direction of the data transfer. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as the acknowledge bit. all other devices on the bus then remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is 0, the master writes to the slave device. if the r/ w bit is 1, the master reads from the slave device. data is sent over the serial bus in a sequence of nine clock pulseseight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high can be interpreted as a stop signal. the number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. when all data bytes are read or written, a stop condition is established. a stop condition is defined by a low-to-high transition on sda while sclk remains high. if the ad7147 encounters a stop condition, it returns to its idle condition, and the address pointer register resets to address 0x00.
ad7147 rev. a | page 36 of 72 sda dev a6 dev a5 dev a4 r/w a7 a6 sclk dev a3 a1 a0 1 26 234 17 18 19 20 25 dev a2 dev a1 dev a0 ack a15 a14 11 16 5678 910 start ad7147-1 device address a9 a8 register address [a15:a8] register address [a7:a0] ack d15 d14 d9 d8 35 27 28 29 34 3736 43 38 44 d1 d0 d7 d6 ack ack 45 46 ack stop dev a6 dev a5 dev a4 123 start t 8 t 7 t 6 t 5 t 4 t 2 t 1 t 3 ad7147-1 device address notes 1. a start condition at the beginning is defined as a high-to-low transition on sda while sclk remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while sclk remains high. 3. 7-bit device address [dev a6:dev a0] = [0 1 0 1 1 x x], where x is a don?t care bit. 4. 16-bit register address [a15:a0] = [x, x, x, x, x, x, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0], where x is a don?t care bit. 5. register address [a15:a8] and register address [a7:a0] are always separated by a low ack bit. 6. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. register data [d15:d8] register data [d7:d0] 0 6663-050 figure 53. example of i 2 c timing for single register write operation writing data over the i 2 c bus the process for writing to the ad7147-1 over the i 2 c bus is shown in figure 53 and figure 55 . the device address is sent over the bus, followed by the r/ w bit being set to 0 and then two bytes of data that contain the 10-bit address of the internal data register to be written. the following bit map shows the upper register address bytes. note that bit 7 to bit 2 in the upper address byte are dont care bits. the address is contained in the 10 lsbs of the register address bytes. msb lsb 7 6 5 4 3 2 1 0 x x x x x x register address bit 9 register address bit 8 the following bit map shows the lower register address bytes. msb lsb 7 6 5 4 3 2 1 0 reg add reg add reg add reg add reg add reg add reg add reg add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the third data byte contains the eight msbs of the data to be written to the internal register. the fourth data byte contains the eight lsbs of data to be written to the internal register. the ad7147-1 address pointer register automatically increments after each write. this allows the master to sequentially write to all registers on the ad7147-1 in the same write transaction. however, the address pointer register does not wrap around after the last address. therefore, any data written to the ad7147-1 after the address pointer has reached its maximum value is discarded. all registers on the ad7147-1 are 16 bits. two consecutive 8-bit data bytes are combined and written to the 16-bit registers. to avoid errors, all writes to the device must contain an even number of data bytes. to finish the transaction, the master generates a stop condition on sdo, or generates a repeat start condition if the master is to maintain control of the bus. reading data over the i 2 c bus to read from the ad7147-1, the address pointer register must first be set to the address of the required internal register. the master performs a write transaction, and then writes to the ad7147-1 to set the address pointer. next, the master outputs a repeat start condition to keep control of the bus, or if this is not possible, ends the write transaction with a stop condition. a read transaction is initiated, with the r/ w bit set to 1. the ad7147-1 supplies the upper eight bits of data from the addressed register in the first readback byte, followed by the lower eight bits in the next byte. this is shown in figure 54 and figure 55 . because the address pointer automatically increments after each read, the ad7147-1 continues to output readback data until the master sends a no acknowledge and stop condition to the bus. if the address pointer reaches its maximum value and the master continues to read from the part, the ad7147-1 repeatedly sends data from the last register that was addressed.
ad7147 rev. a | page 37 of 72 sda dev a6 dev a5 dev a4 r/w a7 a6 sclk dev a3 a1 a0 1 26 234 17 18 19 20 25 dev a2 dev a1 dev a0 ack a15 a14 11 16 5678 910 ad7147-1 device address a9 a8 register address [a15:a8] register address [a7:a0] ack 35 28 30 34 3736 44 38 45 d1 d0 d7 d6 sr ack 46 p dev a6 dev a5 dev a4 123 t 8 t 7 t 6 t 5 t 4 t 2 t 1 t 3 ad7147-1 device address ack 27 ad7147-1 device address dev a6 dev a5 dev a1 dev a0 r/w 29 39 35 28 30 34 3736 44 38 45 d1 d0 d7 d6 s ack 46 p t 5 t 4 ad7147-1 device address dev a6 dev a5 dev a1 dev a0 r/w 29 39 p using repeated start separate read and w rite transactions ack ack start register data [d7:d0] register data [d7:d0] notes 1. a start condition at the beginning is defined as a high-to-low transition on sda while sclk remains high. 2. a stop condition at the end is defined as a low-to-high transition on sda while sclk remains high. 3. the master generates the ack at the end of the readback to signal that it does not want additional data. 4. 7-bit device address [dev a6:dev a0] = [0 1 0 1 1 x x], where the two lsb xs are don't care bits. 5. 16-bit register address [a15:a0] = [x, x, x, x, x, x, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0], where the upper lsb xs are do n?t care bits. 6. register address [a15:a8] and register address [a7:a0] are always separated by low ack bits. 7. register data [d15:d8] and register data [d7:d0] are always separated by a low ack bit. 8. the r/w bit is set to a1 to indicate a readback operation. 06663-051 figure 54. example of i 2 c timing for single regi ster readback operation ack write output from master s p p ack ack = no acknowledge bit ack ack w ack ack ack ack read (using repeated start) s ack ack w ack ack r sr p ack ack read (write transaction sets up register addr ess) s ack ack w ack ack r p s ack ack output from ad7147-1 s = start bit p = stop bit sr = repeated start bit ack = acknowledge bit 6-bit device address register addr [15:8] register addr [7:0] write data high byte [15:8] write data low byte [7:0] write data high byte [15:8] write data low byte [7:0] read data high byte [15:8] read data low byte [7:0] read data high byte [15:8] read data low byte [7:0] 6-bit device address register addr low byte register addr high byte 6-bit device address read data low byte [7:0] read data high byte [15:8] read data low byte [7:0] read data high byte [15:8] 6-bit device address register addr low byte register addr high byte 6-bit device address 0 6663-052 figure 55. example of sequential i 2 c write and readback operations v drive input the supply voltage for the pins (sdo, sdi, sclk, sda, cs , int , and gpio) associated with both the i 2 c and spi serial interfaces is supplied from the v drive pin and is separate from the main v cc supply. this allows the ad7147 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the ad7147 without the need for external level- shifters. the v drive pin can be connected to voltage supplies as low as 1.65 v and as high as v cc .
ad7147 rev. a | page 38 of 72 pcb design guidelines capacitive sensor board me chanical specifications table 19. parameter symbol min typ max unit distance from edge of any sensor to edge of grounded metal object d 1 0.1 mm distance between sensor edges 1 d 2 = d 3 = d 4 0 mm distance between bottom of sensor board and controller board or grounded metal casing 2 d 5 1.0 mm 1 the distance is dependent on the application and the position of the switches relative to each other and with respect to the u sers finger position and handling. adjacent sensors with no space between them are implemented differentially. 2 the 1.0 mm specification is intended to prevent direct sensor board contact with any conductive material. this specification, however, does not guarantee an absence of emi coupling from the controller board to the sensors. to avoid potential emi-coupling issues, place a grounded metal shield between the capacitive sensor board and the main controller board, as shown in figure 58. slider buttons capacitive sensor printed circuit d 1 d 3 d 4 8-way switch metal object d 2 06663-053 figure 56. capacitive se nsor board, top view d 5 capacitive sensor board controller printed circuit board or metal casing 06663-054 figure 57. capacitive se nsor board, side view d 5 capacitive sensor board grounded metal shield controller printed circuit board or metal casing 06663-055 figure 58. capacitive sensor board with grounded shield chip scale packages the lands on the chip scale package (cp-24-3) are rectangular. the pcb pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. center the land on the pad to maximize the solder joint size. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. to avoid shorting, provide a clear- ance of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the pcb. thermal vias can be used on the pcb thermal pad to improve the thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz copper to plug the via. connect the pcb thermal pad to gnd.
ad7147 rev. a | page 39 of 72 po wer-up sequence to power up the ad7147, use the following sequence when initially developing the ad7147 and microprocessor serial interface: 1. turn on the power supplies to the ad7147. 2. write to the bank 2 registers at address 0x080 through address 0x0df. these registers are contiguous; therefore, a sequential register write sequence can be applied. note that the bank 2 register values are unique for each application. register values come from characterization of the sensor in the application. 3. write to the bank 1 registers at address 0x000 through address 0x007, outlined as follows. these registers are contiguous; therefore, a sequential register write sequence can be applied (see figure 50 and figure 55 ). caution: at this time, address 0x001 must remain set to a default value of 0x0000 during this contiguous write operation. register values: address 0x000 = 0x82b2 address 0x001 = 0x000 address 0x002 = 0x3230 (depends on number of conversion stages used) address 0x003 = 0x419 ad dress 0x004 = 832 address 0x005 = interrupt enable register (depends on required interrupt behavior) address 0x006 = interrupt enable register (depends on required interrupt behavior) address 0x007 = interrupt enable register (depends on required interrupt behavior) 4. write to the bank 1 register, address 0x001 = 0x0fff (depends on number of conversion stages used). 5. read back the corresponding interrupt status register at address 0x008, address 0x009, or address 0x00a. this is determined by the interrupt output configuration, as explained in the interrupt output section. note that the specific registers required to be read back depend on each application. for buttons, the interrupt status registers are read back while other sensors read data back from the ad7147 according to the slider or wheel algorithms requirements. analog devices can provide this information after the user develops the sensor board. 6. repeat step 5 every time int is asserted. first conversion sequence conversion stage 0 conversion stages disabled 1234567891011012 91011012 910110 1 second conversion sequence third conversion sequence power host serial interface ad7147 int 0 6663-056 figure 59. recommended start-up sequence
ad7147 rev. a | page 40 of 72 typical application circuits scroll wheel plane around sensors connected to ac shield button button button button 1 cin6 2 cin7 3 cin8 4 cin9 5 cin10 6 cin11 gpio 18 int 17 cs 16 sclk 15 sdi 14 sdo 13 7 cin12 8 ac shield 9 bias 10 gnd 11 v cc 12 v drive cin5 24 cin4 23 cin3 22 cin2 21 cin1 20 cin0 19 ad7147 int ss sck mosi miso v host host with spi interface v cc 2.7v to 3.6v 1.8v 1 f to 10 f (optional) 0.1 f 100nf v drive 2.2k ? 06663-057 sensor pcb figure 60. typical application circuit with spi interface 1 cin6 2 cin7 3 cin8 4 cin9 5 cin10 6 cin11 gpio 18 int 17 add1 16 sclk 15 add0 14 sda 13 7 cin12 8 ac shield 9 bias 10 gnd 11 v cc 12 v drive cin5 24 cin4 23 cin3 22 cin2 21 cin1 20 cin0 19 ad7147-1 int sck sdo host with i 2 c interface 2.2k ? 2.2k ? 2.2k ? slider button button button 2-way switch v drive v drive v drive v cc 2.7v to 3.6v 1 f to 10 f (optional) 0.1 f 100nf connect plane around sensors to ac shield 0 6663-058 figure 61. typical application circuit with i 2 c interface
ad7147 rev. a | page 41 of 72 register map the ad7147 address space is divided into three register banks, referred to as bank 1, bank 2, and bank 3. figure 62 illustrates the division of these banks. bank 3 registers contain the results of each conversion stage. these registers automatically update at the end of each conversion sequence. although these registers are primarily used by the ad7147 internal data processing, they are accessible by the host processor for additional external data processing, if desired. bank 1 registers contain control registers, cdc conversion control registers, interrupt enable registers, interrupt status registers, cdc 16-bit conversion data registers, device id registers, and proximity status registers. default values are undefined for bank 2 registers and bank 3 registers until after power-up and configuration of the bank 2 registers. bank 2 registers contain the configuration registers used to configure the individual cinx inputs for each conversion stage. initialize the bank 2 configuration registers immediately after power-up to obtain valid cdc conversion result data. 06663-059 bank 1 registers addr 0x000 addr 0x018 addr 0x001 addr 0x005 addr 0x008 addr 0x00b addr 0x017 addr 0x7f0 bank 2 registers addr 0x080 addr 0x0b8 addr 0x0c0 addr 0x0c8 addr 0x0d0 addr 0x0d8 addr 0x088 addr 0x090 addr 0x098 addr 0x0a0 addr 0x0a8 addr 0x0b0 bank 3 registers addr 0x0e0 addr 0x088 addr 0x090 addr 0x098 addr 0x0a0 addr 0x0a8 addr 0x042 addr 0x043 invalid do not access proximity status register (1 register) invalid do not access device id register (1 register) cdc 16-bit conversion data (12 registers) interrupt status (3 registers) interrupt enable (3 registers) calibration and setup (4 registers) setup control (1 register) 96 registers 432 registers stage7 configuration (8 registers) stage6 configuration (8 registers) stage8 configuration (8 registers) stage9 configuration (8 registers) stage10 configuration (8 registers) stage11 configuration (8 registers) stage5 configuration (8 registers) stage4 configuration (8 registers) stage3 configuration (8 registers) stage2 configuration (8 registers) stage1 configuration (8 registers) stage0 configuration (8 registers) stage7 results (36 registers) stage6 results (36 registers) stage8 results (36 registers) stage9 results (36 registers) stage10 results (36 registers) stage11 results (36 registers) stage5 results (36 registers) stage4 results (36 registers) stage3 results (36 registers) stage2 results (36 registers) stage1 results (36 registers) stage0 results (36 registers) 26 registers addr 0x0b8 addr 0x0c0 addr 0x0c8 addr 0x0d0 addr 0x28f addr 0x0b0 figure 62. layout of bank 1, bank 2, and bank 3 registers
ad7147 rev. a | page 42 of 72 detailed register descriptions bank 1 registers all addresses and default values are expressed in hexadecimal. table 20. pwr_control register address data bit default value type name description 0x000 [1:0] 0 r/w power_mode operating modes 00 = full power mode (normal operation, cdc conversions approximately every 36 ms) 01 = full shutdown mode (no cdc conversions) 10 = low power mode (automatic wake-up operation) 11 = full shutdown mode (no cdc conversions) [3:2] 0 r/w lp_conv_delay low power mode conversion delay 00 = 200 ms 01 = 400 ms 10 = 600 ms 11 = 800 ms [7:4] 0 r/w sequence_stage_num numb er of stages in sequence (n + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence maximum value = 1011 = 12 conversion stages per sequence [9:8] 0 r/w decimation adc decimation factor 00 = decimate by 256 01 = decimate by 128 10 = decimate by 64 11 = decimate by 64 [10] 0 r/w sw_reset software reset control (self-clearing) 1 = resets all registers to default values [11] 0 r/w int_pol interrupt polarity control 0 = active low 1 = active high [12] 0 r/w ext_source excitation source control 0 = enable excitation source to cinx pins 1 = disable excitation source to cinx pins [13] 0 unused set to 0 [15:14] 0 r/w cdc_bias cdc bias current control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50%
ad7147 rev. a | page 43 of 72 table 21. stage_cal_en register address data bit default value type name description 0x001 [0] 0 r/w stage0_cal_en stage0 calibration enable 0 = disable 1 = e n a b l e [1] 0 r/w stage1_cal_en stage1 calibration enable 0 = disable 1 = e n a b l e [2] 0 r/w stage2_cal_en stage2 calibration enable 0 = disable 1 = e n a b l e [3] 0 r/w stage3_cal_en stage3 calibration enable 0 = disable 1 = e n a b l e [4] 0 r/w stage4_cal_en stage4 calibration enable 0 = disable 1 = e n a b l e [5] 0 r/w stage5_cal_en stage5 calibration enable 0 = disable 1 = e n a b l e [6] 0 r/w stage6_cal_en stage6 calibration enable 0 = disable 1 = e n a b l e [7] 0 r/w stage7_cal_en stage7 calibration enable 0 = disable 1 = e n a b l e [8] 0 r/w stage8_cal_en stage8 calibration enable 0 = disable 1 = e n a b l e [9] 0 r/w stage9_cal_en stage9 calibration enable 0 = disable 1 = e n a b l e [10] 0 r/w stage10_cal_en stage10 calibration enable 0 = disable 1 = e n a b l e [11] 0 r/w stage11_cal_en stage11 calibration enable 0 = disable 1 = e n a b l e [13:12] 0 r/w avg_fp_skip full power mode skip control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples [15:14] 0 r/w avg_lp_skip low power mode skip control 00 = use all samples 01 = skip one sample 10 = skip two samples 11 = skip three samples
ad7147 rev. a | page 44 of 72 table 22. amb_comp_ctrl0 register address data bit default value type name description 0x002 [3:0] 0 r/w ff_skip_cnt fast filter skip control (n + 1) 0000 = no sequence of results is skipped 0001 = one sequence of results is skipped for every one allowed into fast fifo 0010 = two sequences of results are skipped for every one allowed into fast fifo 1011 = maximum value = 12 sequences of results are skipped for every one allowed into fast fifo [7:4] f r/w fp_proximity_cnt calibration disable period in full power mode = fp_proximity_cnt 16 time for one conversion sequence in full power mode [11:8] f r/w lp_proximity_cnt calibration disable period in low power mode = lp_proximity_cnt 4 time for one conversion sequence in low power mode [13:12] 0 r/w pwr_down_timeout full power to low power mode timeout control 00 = 1.25 (fp_proximity_cnt) 01 = 1.50 (fp_proximity_cnt) 10 = 1.75 (fp_proximity_cnt) 11 = 2.00 (fp_proximity_cnt) [14] 0 r/w forced_cal forced calibration control 0 = n o r m a l o p e r a t i o n 1 = forces all conversion stages to recalibrate [15] 0 r/w conv_reset conversion reset control (self-clearing) 0 = n o r m a l o p e r a t i o n 1 = resets the conversion sequence to stage0 table 23. amb_comp_ctrl1 register address data bit default value type name description 0x003 [7:0] 64 r/w proximity_recal_lvl proximity recalibration level; the value is multiplied by 16 to determine actual recalibration level [13:8] 1 r/w proximity_detection_rate proximity detection rate; the value is multiplied by 16 to determine actual detection rate [15:14] 0 r/w slow_filter_update _lvl slow filter update level table 24. amb_comp_ctrl2 register address data bit default value type name description 0x004 [9:0] 3ff r/w fp_proximity_recal full power mode proximity recalibration time control [15:10] 3f r/w lp_proximity_recal low power mode proximity recalibration time control
ad7147 rev. a | page 45 of 72 table 25. stage_low_int_enable register address data bit default value type name description 0x005 [0] 0 r/w stage0_low_int_enable stage0 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 low threshold is exceeded [1] 0 r/w stage1_low_int_enable stage1 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage1 low threshold is exceeded [2] 0 r/w stage2_low_int_enable stage2 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage2 low threshold is exceeded [3] 0 r/w stage3_low_int_enable stage3 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage3 low threshold is exceeded [4] 0 r/w stage4_low_int_enable stage4 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage4 low threshold is exceeded [5] 0 r/w stage5_low_int_enable stage5 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage5 low threshold is exceeded [6] 0 r/w stage6_low_int_enable stage6 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage6 low threshold is exceeded [7] 0 r/w stage7_low_int_enable stage7 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage7 low threshold is exceeded [8] 0 r/w stage8_low_int_enable stage8 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage8 low threshold is exceeded [9] 0 r/w stage9_low_int_enable stage9 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage9 low threshold is exceeded [10] 0 r/w stage10_low_int_enable stage10 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage10 low threshold is exceeded [11] 0 r/w stage11_low_int_enable stage11 low interrupt enable 0 = interrupt source disabled 1 = int asserted if stage11 low threshold is exceeded [13:12] 0 r/w gpio_setup gpio setup 00 = disable gpio pin 01 = configure gpio as an input 10 = configure gpio as an active low output 11 = configure gpio as an active high output [15:14] 0 r/w gpio_input_config gpio input configuration 00 = triggered on negative level 01 = triggered on positive edge 10 = triggered on negative edge 11 = triggered on positive level
ad7147 rev. a | page 46 of 72 table 26. stage_high_int_enable register address data bit default value type name description 0x006 [0] 0 r/w stage0_high_int_enable stage0 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage0 high threshold is exceeded [1] 0 r/w stage1_high_int_enab le stage1 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage1 high threshold is exceeded [2] 0 r/w stage2_high_int_enab le stage2 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage2 high threshold is exceeded [3] 0 r/w stage3_high_int_enab le stage3 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage3 high threshold is exceeded [4] 0 r/w stage4_high_int_enab le stage4 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage4 high threshold is exceeded [5] 0 r/w stage5_high_int_enab le stage5 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage5 high threshold is exceeded [6] 0 r/w stage6_high_int_enab le stage6 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage6 high threshold is exceeded [7] 0 r/w stage7_high_int_enab le stage7 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage7 high threshold is exceeded [8] 0 r/w stage8_high_int_enab le stage8 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage8 high threshold is exceeded [9] 0 r/w stage9_high_int_enable st age9 sensor high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage9 high threshold is exceeded [10] 0 r/w stage10_high_int_enable stage10 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage10 high threshold is exceeded [11] 0 r/w stage11_high_int_enable stage11 high interrupt enable 0 = interrupt source disabled 1 = int asserted if stage11 high threshold is exceeded [15:12] unused set to 0
ad7147 rev. a | page 47 of 72 table 27. stage_complete_int_enable register address data bit default value type name description 0x007 [0] 0 r/w stage0_complete_int_enab le stage0 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage0 conversion [1] 0 r/w stage1_complete_int_enable stage1 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage1 conversion [2] 0 r/w stage2_complete_int_enable stage2 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage2 conversion [3] 0 r/w stage3_complete_int_enable stage3 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage3 conversion [4] 0 r/w stage4_complete_int_enable stage4 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage4 conversion [5] 0 r/w stage5_complete_int_enable stage5 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage5 conversion [6] 0 r/w stage6_complete_int_enable stage6 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage6 conversion [7] 0 r/w stage7_complete_int_enable stage7 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage7 conversion [8] 0 r/w stage8_complete_int_enable stag e8 conversion complete interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage8 conversion [9] 0 r/w stage9_complete_int_enable stage9 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage9 conversion [10] 0 r/w stage10_complete_int_enable stage10 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage10 conversion [11] 0 r/w stage11_complete_int_enable stage11 conversion interrupt control 0 = interrupt source disabled 1 = int asserted at completion of stage11 conversion [12] 0 r/w gpio_int_enable interrupt co ntrol when gpio input pin changes level 0 = disabled 1 = enabled [15:13] unused set to 0
ad7147 rev. a | page 48 of 72 table 28. stage_low_int_status register 1 address data bit default value type name description 0x008 [0] 0 r stage0_low_int_status stage0 cdc conversion low limit interrupt result 1 = indicates stage0_low_threshold value was exceeded [1] 0 r stage1_low_int_status stage1 cdc conversion low limit interrupt result 1 = indicates stage1_low_threshold value was exceeded [2] 0 r stage2_low_int_status stage2 cdc conversion low limit interrupt result 1 = indicates stage2_low_threshold value was exceeded [3] 0 r stage3_low_int_status stage3 cdc conversion low limit interrupt result 1 = indicates stage3_low_threshold value was exceeded [4] 0 r stage4_low_int_status stage4 cdc conversion low limit interrupt result 1 = indicates stage4_low_threshold value was exceeded [5] 0 r stage5_low_int_status stage5 cdc conversion low limit interrupt result 1 = indicates stage5_low_threshold value was exceeded [6] 0 r stage6_low_int_status stage6 cdc conversion low limit interrupt result 1 = indicates stage6_low_threshold value was exceeded [7] 0 r stage7_low_int_status stage7 cdc conversion low limit interrupt result 1 = indicates stage7_low_threshold value was exceeded [8] 0 r stage8_low_int_status stage8 cdc conversion low limit interrupt result 1 = indicates stage8_low_threshold value was exceeded [9] 0 r stage9_low_int_status stage9 cdc conversion low limit interrupt result 1 = indicates stage9_low_threshold value was exceeded [10] 0 r stage10_low_int_status stage10 cdc conversion low limit interrupt result 1 = indicates stage10_low_threshold value was exceeded [11] 0 r stage11_low_int_status stage11 cdc conversion low limit interrupt result 1 = indicates stage11_low_threshold value was exceeded [15:12] unused set to 0 1 registers self-clear to 0 after read back if the limits are not exceeded.
ad7147 rev. a | page 49 of 72 table 29. stage_high_int_status register 1 address data bit default value type name description 0x009 [0] 0 r stage0_high_int_status stage0 cdc conversion high limit interrupt result 1 = indicates stage0_high_threshold value was exceeded [1] 0 r stage1_high_int_status stage1 cdc conversion high limit interrupt result 1 = indicates stage1_high_threshold value was exceeded [2] 0 r stage2_high_int_status stage2 cdc conversion high limit interrupt result 1 = indicates stage2_high_threshold value was exceeded [3] 0 r stage3_high_int_status stage3 cdc conversion high limit interrupt result 1 = indicates stage3_high_threshold value was exceeded [4] 0 r stage4_high_int_status stage4 cdc conversion high limit interrupt result 1 = indicates stage4_high_threshold value was exceeded [5] 0 r stage5_high_int_status stage5 cdc conversion high limit interrupt result 1 = indicates stage5_high_threshold value was exceeded [6] 0 r stage6_high_int_status stage6 cdc conversion high limit interrupt result 1 = indicates stage6_high_threshold value was exceeded [7] 0 r stage7_high_int_status stage7 cdc conversion high limit interrupt result 1 = indicates stage7_high_threshold value was exceeded [8] 0 r stage8_high_int_status stage8 cdc conversion high limit interrupt result 1 = indicates stage8_high_threshold value was exceeded [9] 0 r stage9_high_int_status stage9 cdc conversion high limit interrupt result 1 = indicates stage9_high_threshold value was exceeded [10] 0 r stage10_high_int_status stage10 cdc conversion high limit interrupt result 1 = indicates stage10_high_threshold value was exceeded [11] 0 r stage11_high_int_status stage11 cdc conversion high limit interrupt result 1 = indicates stage11_high_threshold value was exceeded [15:12] unused set to 0 1 registers self-clear to 0 after read back if the limits are not exceeded.
ad7147 rev. a | page 50 of 72 table 30. stage_complete_int_status register 1 address data bit default value type name description 0x00a [0] 0 r stage0_complete_int_status stage0 conversion complete register interrupt status 1 = indicates stage0 conversion completed [1] 0 r stage1_complete_int_status stage1 conversion complete register interrupt status 1 = indicates stage1 conversion completed [2] 0 r stage2_complete_int_status stage2 conversion complete register interrupt status 1 = indicates stage2 conversion completed [3] 0 r stage3_complete_int_status stage3 conversion complete register interrupt status 1 = indicates stage3 conversion completed [4] 0 r stage4_complete_int_status stage4 conversion complete register interrupt status 1 = indicates stage4 conversion completed [5] 0 r stage5_complete_int_status stage5 conversion complete register interrupt status 1 = indicates stage5 conversion completed [6] 0 r stage6_complete_int_status stage6 conversion complete register interrupt status 1 = indicates stage6 conversion completed [7] 0 r stage7_complete_int_status stage7 conversion complete register interrupt status 1 = indicates stage7 conversion completed [8] 0 r stage8_complete_int_status stage8 conversion complete register interrupt status 1 = indicates stage8 conversion completed [9] 0 r stage9_complete_int_status stage9 conversion complete register interrupt status 1 = indicates stage9 conversion completed [10] 0 r stage10_complete_int_status stage10 conversion complete register interrupt status 1 = indicates stage10 conversion completed [11] 0 r stage11_complete_int_status stage11 conversion complete register interrupt status 1 = indicates stage11 conversion completed [12] 0 r gpio_int_status gpio input pin status 1 = indicates level on gpio pin has changed [15:13] unused set to 0 1 registers self-clear to 0 after read back if the limits are not exceeded. table 31. cdc 16-bit conversion data registers address data bit default value type name description 0x00b [15:0] 0 r cdc_result_s0 stage0 cdc 16-bit conversion data 0x00c [15:0] 0 r cdc_result_s1 stage1 cdc 16-bit conversion data 0x00d [15:0] 0 r cdc_result_s2 stage2 cdc 16-bit conversion data 0x00e [15:0] 0 r cdc_result_s3 stage3 cdc 16-bit conversion data 0x00f [15:0] 0 r cdc_result_s4 stage4 cdc 16-bit conversion data 0x010 [15:0] 0 r cdc_result_s5 stage5 cdc 16-bit conversion data 0x011 [15:0] 0 r cdc_result_s6 stage6 cdc 16-bit conversion data 0x012 [15:0] 0 r cdc_result_s7 stage7 cdc 16-bit conversion data 0x013 [15:0] 0 r cdc_result_s8 stage8 cdc 16-bit conversion data 0x014 [15:0] 0 r cdc_result_s9 stage9 cdc 16-bit conversion data 0x015 [15:0] 0 r cdc_result_s10 stage10 cdc 16-bit conversion data 0x016 [15:0] 0 r cdc_result_s11 stage11 cdc 16-bit conversion data
ad7147 rev. a | page 51 of 72 table 32. device id register address data bit default value type name description 0x017 [3:0] 0 r revision_code revision code [15:4] 147 r devid device id = 0001 0100 0111 table 33. proximity status register address data bit default value type name description 0x042 [0] 0 r stage0_proximity_status stage0 proximity status register 1 = indicates proximity has been detected on stage0 [1] 0 r stage1_proximity_status stage1 proximity status register 1 = indicates proximity has been detected on stage1 [2] 0 r stage2_proximity_status stage2 proximity status register 1 = indicates proximity has been detected on stage2 [3] 0 r stage3_proximity_status stage3 proximity status register 1 = indicates proximity has been detected on stage3 [4] 0 r stage4_proximity_status stage4 proximity status register 1 = indicates proximity has been detected on stage4 [5] 0 r stage5_proximity_status stage5 proximity status register 1 = indicates proximity has been detected on stage5 [6] 0 r stage6_proximity_status stage6 proximity status register 1 = indicates proximity has been detected on stage6 [7] 0 r stage7_proximity_status stage7 proximity status register 1 = indicates proximity has been detected on stage7 [8] 0 r stage8_proximity_status stage8 proximity status register 1 = indicates proximity has been detected on stage8 [9] 0 r stage9_proximity_status stage9 proximity status register 1 = indicates proximity has been detected on stage9 [10] 0 r stage10_proximity_status stage10 proximity status register 1 = indicates proximity has been detected on stage10 [11] 0 r stage11_proximity_status stage11 proximity status register 1 = indicates proximity has been detected on stage11 [15:12] unused set to 0
ad7147 rev. a | page 52 of 72 bank 2 registers all address values are expressed in hexadecimal. table 34. stagex_connection[6:0] re gister description (x = 0 to 11) data bit default value type name description [1:0] x r/w cin0_connection_setup cin0 connection setup 00 = cin0 not connected to cdc inputs 01 = cin0 connected to cdc negative input 10 = cin0 connected to cdc positive input 11 = cin0 connected to bias (connect unused cinx inputs) [3:2] x r/w cin1_connection_setup cin1 connection setup 00 = cin1 not connected to cdc inputs 01 = cin1 connected to cdc negative input 10 = cin1 connected to cdc positive input 11 = cin1 connected to bias (connect unused cinx inputs) [5:4] x r/w cin2_connection_setup cin2 connection setup 00 = cin2 not connected to cdc inputs 01 = cin2 connected to cdc negative input 10 = cin2 connected to cdc positive input 11 = cin2 connected to bias (connect unused cinx inputs) [7:6] x r/w cin3_connection_setup cin3 connection setup 00 = cin3 not connected to cdc inputs 01 = cin3 connected to cdc negative input 10 = cin3 connected to cdc positive input 11 = cin3 connected to bias (connect unused cinx inputs) [9:8] x r/w cin4_connection_setup cin4 connection setup 00 = cin4 not connected to cdc inputs 01 = cin4 connected to cdc negative input 10 = cin4 connected to cdc positive input 11 = cin4 connected to bias (connect unused cinx inputs) [11:10] x r/w cin5_connection_setup cin5 connection setup 00 = cin5 not connected to cdc inputs 01 = cin5 connected to cdc negative input 10 = cin5 connected to cdc positive input 11 = cin5 connected to bias (connect unused cinx inputs) [13:12] x r/w cin6_connection_setup cin6 connection setup 00 = cin6 not connected to cdc inputs 01 = cin6 connected to cdc negative input 10 = cin6 connected to cdc positive input 11 = cin6 connected to bias (connect unused cinx inputs) [15:14] x unused set to 0
ad7147 rev. a | page 53 of 72 table 35. stagex_connection[12:7] register description (x = 0 to 11) data bit default value type name description [1:0] x r/w cin7_connection_setup cin7 connection setup 00 = cin7 not connected to cdc inputs 01 = cin7 connected to cdc negative input 10 = cin7 connected to cdc positive input 11 = cin7 connected to bias (connect unused cinx inputs) [3:2] x r/w cin8_connection_setup cin8 connection setup 00 = cin8 not connected to cdc inputs 01 = cin8 connected to cdc negative input 10 = cin8 connected to cdc positive input 11 = cin8 connected to bias (connect unused cinx inputs) [5:4] x r/w cin9_connection_setup cin9 connection setup 00 = cin9 not connected to cdc inputs 01 = cin9 connected to cdc negative input 10 = cin9 connected to cdc positive input 11 = cin9 connected to bias (connect unused cinx inputs) [7:6] x r/w cin10_connection_setup cin10 connection setup 00 = cin10 not connected to cdc inputs 01 = cin10 connected to cdc negative input 10 = cin10 connected to cdc positive input 11 = cin10 connected to bias (connect unused cinx inputs) [9:8] x r/w cin11_connection_setup cin11 connection setup 00 = cin11 not connected to cdc inputs 01 = cin11 connected to cdc negative input 10 = cin11 connected to cdc positive input 11 = cin11 connected to bias (connect unused cinx inputs) [11:10] x r/w cin12_connection_setup cin12 connection setup 00 = cin12 not connected to cdc inputs 01 = cin12 connected to cdc negative input 10 = cin12 connected to cdc positive input 11 = cin12 connected to bias (connect unused cinx inputs) [13:12] x r/w se_connection_setup sing le-ended measurement connection setup 00 = do not use 01 = use when one cinx connected to cdc positive input, single-ended measurements only 10 = use when one cinx connected to cdc negative input, single-ended measurements only 11 = differential connection to cdc [14] x r/w neg_afe_offset_disable negative afe offset enable control 0 = enable 1 = disable [15] x r/w pos_afe_offset_disable po sitive afe offset enable control 0 = enable 1 = disable
ad7147 rev. a | page 54 of 72 table 36. stagex_afe_offset register description (x = 0 to 11) data bit default value type name description [5:0] x r/w neg_afe_offset negative afe offset setting (20 pf range) 1 lsb value = 0.32 pf of offset [6] x unused set to 0 [7] x r/w neg_afe_offset_swap negative afe offset swap control 0 = neg_afe_offset applied to cdc negative input 1 = neg_afe_offset applied to cdc positive input [13:8] x r/w pos_afe_offset positive afe offset setting (20 pf range) 1 lsb value = 0.32 pf of offset [14] x unused set to 0 [15] x r/w pos_afe_offset_swap positive afe offset swap control 0 = pos_afe_offset applied to cdc positive input 1 = pos_afe_offset applied to cdc negative input table 37. stagex_sensitivity register description (x = 0 to 11) data bit default value type name description [3:0] x r/w neg_threshold_sensitivity negative threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [6:4] x r/w neg_peak_detect ne gative peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [7] x r/w unused set to 0 [11:8] x r/w pos_threshold_sensitivity positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [14:12] x r/w pos_peak_detect positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level [15] x r/w unused set to 0
ad7147 rev. a | page 55 of 72 table 38. stage0 to stage11 configuration registers address data bit default type name description 0x080 [15:0] x r/w stage0_connection[6:0] stage0 cin[6:0] connection setup (see table 34 ) 0x081 [15:0] x r/w stage0_connection[12:7] stage0 cin[12:7] connection setup (see table 35 ) 0x082 [15:0] x r/w stage0_afe_offset stage0 afe offset control (see table 36 ) 0x083 [15:0] x r/w stage0_sensitivity stage0 sensitivity control (see table 37 ) 0x084 [15:0] x r/w stage0_offset_low stage0 initial offset low value 0x085 [15:0] x r/w stage0_offset_high stage0 initial offset high value 0x086 [15:0] x r/w stage0_offset_high_clamp stage0 offset high clamp value 0x087 [15:0] x r/w stage0_offset_low_clamp stage0 offset low clamp value 0x088 [15:0] x r/w stage1_connection[6:0] stage1 cin[6:0] connection setup (see table 34 ) 0x089 [15:0] x r/w stage1_connection[12:7] stage1 cin[12:7] connection setup (see table 35 ) 0x08a [15:0] x r/w stage1_afe_offset stage1 afe offset control (see table 36 ) 0x08b [15:0] x r/w stage1_sensitivity stage1 sensitivity control (see table 37 ) 0x08c [15:0] x r/w stage1_offset_low stage1 initial offset low value 0x08d [15:0] x r/w stage1_offset_high stage1 initial offset high value 0x08e [15:0] x r/w stage1_offset_high_clamp stage1 offset high clamp value 0x08f [15:0] x r/w stage1_offset_low_clamp stage1 offset low clamp value 0x090 [15:0] x r/w stage2_connection[6:0] stage2 cin[6:0] connection setup (see table 34 ) 0x091 [15:0] x r/w stage2_connection[12:7] stage2 cin[12:7] connection setup (see table 35 ) 0x092 [15:0] x r/w stage2_afe_offset stage2 afe offset control (see table 36 ) 0x093 [15:0] x r/w stage2_sensitivity stage2 sensitivity control (see table 37 ) 0x094 [15:0] x r/w stage2_offset_low stage2 initial offset low value 0x095 [15:0] x r/w stage2_offset_high stage2 initial offset high value 0x096 [15:0] x r/w stage2_offset_high_clamp stage2 offset high clamp value 0x097 [15:0] x r/w stage2_offset_low_clamp stage2 offset low clamp value 0x098 [15:0] x r/w stage3_connection[6:0] stage3 cin[6:0] connection setup (see table 34 ) 0x099 [15:0] x r/w stage3_connection[12:7] stage3 cin[12:7] connection setup (see table 35 ) 0x09a [15:0] x r/w stage3_afe_offset stage3 afe offset control (see table 36 ) 0x09b [15:0] x r/w stage3_sensitivity stage3 sensitivity control (see table 37 ) 0x09c [15:0] x r/w stage3_offset_low stage3 initial offset low value 0x09d [15:0] x r/w stage3_offset_high stage3 initial offset high value 0x09e [15:0] x r/w stage3_offset_high_clamp stage3 offset high clamp value 0x09f [15:0] x r/w stage3_offset_low_clamp stage3 offset low clamp value 0x0a0 [15:0] x r/w stage4_connection[6: 0] stage4 cin[6:0] connection setup (see table 34 ) 0x0a1 [15:0] x r/w stage4_connection[12: 7] stage4 cin[12:7] connection setup (see table 35 ) 0x0a2 [15:0] x r/w stage4_afe_offset stage4 afe offset control (see table 36 ) 0x0a3 [15:0] x r/w stage4_sensitivity stage4 sensitivity control (see table 37 ) 0x0a4 [15:0] x r/w stage4_offset_low stage4 initial offset low value 0x0a5 [15:0] x r/w stage4_offset_high stage4 initial offset high value 0x0a6 [15:0] x r/w stage4_offset_high_clamp stage4 offset high clamp value 0x0a7 [15:0] x r/w stage4_offset_low_clamp stage4 offset low clamp value 0x0a8 [15:0] x r/w stage5_connection[6: 0] stage5 cin[6:0] connection setup (see table 34 ) 0x0a9 [15:0] x r/w stage5_connection[12: 7] stage5 cin[12:7] connection setup (see table 35 ) 0x0aa [15:0] x r/w stage5_afe_offset stage5 afe offset control (see table 36 ) 0x0ab [15:0] x r/w stage5_sensitivity stage5 sensitivity control (see table 37 ) 0x0ac [15:0] x r/w stage5_offset_low stage5 initial offset low value 0x0ad [15:0] x r/w stage5_offset_high stage5 initial offset high value 0x0ae [15:0] x r/w stage5_offset_high_clamp stage5 offset high clamp value 0x0af [15:0] x r/w stage5_offset_low_clamp stage5 offset low clamp value
ad7147 rev. a | page 56 of 72 address data bit default type name description 0x0b0 [15:0] x r/w stage6_connection[6: 0] stage6 cin[6:0] connection setup (see table 34 ) 0x0b1 [15:0] x r/w stage6_connection[12: 7] stage6 cin[12:7]connection setup (see table 35 ) 0x0b2 [15:0] x r/w stage6_afe_offset stage6 afe offset control (see table 36 ) 0x0b3 [15:0] x r/w stage6_sensitivity stage6 sensitivity control (see table 37 ) 0x0b4 [15:0] x r/w stage6_offset_low stage6 initial offset low value 0x0b5 [15:0] x r/w stage6_offset_high stage6 initial offset high value 0x0b6 [15:0] x r/w stage6_offset_high_clamp stage6 offset high clamp value 0x0b7 [15:0] x r/w stage6_offset_low_clamp stage6 offset low clamp value 0x0b8 [15:0] x r/w stage7_connection[6: 0] stage7 cin[6:0] connection setup (see table 34 ) 0x0b9 [15:0] x r/w stage7_connection[12: 7] stage7 cin[12:7] connection setup (see table 35 ) 0x0ba [15:0] x r/w stage7_afe_offset stage7 afe offset control (see table 36 ) 0x0bb [15:0] x r/w stage7_sensitivity stage7 sensitivity control (see table 37 ) 0x0bc [15:0] x r/w stage7_offset_low stage7 initial offset low value 0x0bd [15:0] x r/w stage7_offset_high stage7 initial offset high value 0x0be [15:0] x r/w stage7_offset_high_clamp stage7 offset high clamp value 0x0bf [15:0] x r/w stage7_offset_low_clamp stage7 offset low clamp value 0x0c0 [15:0] x r/w stage8_connection[6: 0] stage8 cin[6:0] connection setup (see table 34 ) 0x0c1 [15:0] x r/w stage8_connection[12: 7] stage8 cin[12:7]connection setup (see table 35 ) 0x0c2 [15:0] x r/w stage8_afe_offset stage8 afe offset control (see table 36 ) 0x0c3 [15:0] x r/w stage8_sensitivity stage8 sensitivity control (see table 37 ) 0x0c4 [15:0] x r/w stage8_offset_low stage8 initial offset low value 0x0c5 [15:0] x r/w stage8_offset_high stage8 initial offset high value 0x0c6 [15:0] x r/w stage8_offset_high_clamp stage8 offset high clamp value 0x0c7 [15:0] x r/w stage8_offset_low_clamp stage8 offset low clamp value 0x0c8 [15:0] x r/w stage9_connection[6: 0] stage9 cin[6:0] connection setup (see table 34 ) 0x0c9 [15:0] x r/w stage9_connection[12: 7] stage9 cin[12:7]connection setup (see table 35 ) 0x0ca [15:0] x r/w stage9_afe_offset stage9 afe offset control (see table 36 ) 0x0cb [15:0] x r/w stage9_sensitivity stage9 sensitivity control (see table 37 ) 0x0cc [15:0] x r/w stage9_offset_low stage9 initial offset low value 0x0cd [15:0] x r/w stage9_offset_high stage9 initial offset high value 0x0ce [15:0] x r/w stage9_offset_high_clamp stage9 offset high clamp value 0x0cf [15:0] x r/w stage9_offset_low_clamp stage9 offset low clamp value 0x0d0 [15:0] x r/w stage10_connection[6 :0] stage10 cin[6:0] connection setup (see table 34 ) 0x0d1 [15:0] x r/w stage10_connection[12: 7] stage10 cin[12:7]connection setup (see table 35 ) 0x0d2 [15:0] x r/w stage10_afe_offset stage10 afe offset control (see table 36 ) 0x0d3 [15:0] x r/w stage10_sensitivity stage10 sensitivity control (see table 37 ) 0x0d4 [15:0] x r/w stage10_offset_low stage10 initial offset low value 0x0d5 [15:0] x r/w stage10_offset_high stage10 initial offset high value 0x0d6 [15:0] x r/w stage10_offset_high_clamp stage10 offset high clamp value 0x0d7 [15:0] x r/w stage10_offset_low_clamp stage10 offset low clamp value 0x0d8 [15:0] x r/w stage11_connection[6 :0] stage11 cin[6:0] connection setup (see table 34 ) 0x0d9 [15:0] x r/w stage11_connection[12: 7] stage11 cin[12:7] connection setup (see table 35 ) 0x0da [15:0] x r/w stage11_afe_offset stage11 afe offset control (see table 36 ) 0x0db [15:0] x r/w stage11_sensitivity stage11 sensitivity control (see table 37 ) 0x0dc [15:0] x r/w stage11_offset_low stage11 initial offset low value 0x0dd [15:0] x r/w stage11_offset_high stage11 initial offset high value 0x0de [15:0] x r/w stage11_offset_high_clamp stage11 offset high clamp value 0x0df [15:0] x r/w stage11_offset_low_clamp stage11 offset low clamp value
ad7147 rev. a | page 57 of 72 bank 3 registers all address values are expressed in hexadecimal. table 39. stage0 results registers address data bit default value type name description 0x0e0 [15:0] x r/w stage0_conv_data stage0 cdc 16-bit conversion data (copy of cdc_result_s0 register) 0x0e1 [15:0] x r/w stage0_ff_word0 stage0 fast fifo word0 0x0e2 [15:0] x r/w stage0_ff_word1 stage0 fast fifo word1 0x0e3 [15:0] x r/w stage0_ff_word2 stage0 fast fifo word2 0x0e4 [15:0] x r/w stage0_ff_word3 stage0 fast fifo word3 0x0e5 [15:0] x r/w stage0_ff_word4 stage0 fast fifo word4 0x0e6 [15:0] x r/w stage0_ff_word5 stage0 fast fifo word5 0x0e7 [15:0] x r/w stage0_ff_word6 stage0 fast fifo word6 0x0e8 [15:0] x r/w stage0_ff_word7 stage0 fast fifo word7 0x0e9 [15:0] x r/w stage0_sf_word0 stage0 slow fifo word0 0x0ea [15:0] x r/w stage0_sf_word1 stage0 slow fifo word1 0x0eb [15:0] x r/w stage0_sf_word2 stage0 slow fifo word2 0x0ec [15:0] x r/w stage0_sf_word3 stage0 slow fifo word3 0x0ed [15:0] x r/w stage0_sf_word4 stage0 slow fifo word4 0x0ee [15:0] x r/w stage0_sf_word5 stage0 slow fifo word5 0x0ef [15:0] x r/w stage0_sf_word6 stage0 slow fifo word6 0x0f0 [15:0] x r/w stage0_sf_word7 stage0 slow fifo word7 0x0f1 [15:0] x r/w stage0_sf_ambient stage0 slow fifo ambient value 0x0f2 [15:0] x r/w stage0_ff_avg stage0 fast fifo average value 0x0f3 [15:0] x r/w stage0_peak_detect_ word0 stage0 peak fifo word0 value 0x0f4 [15:0] x r/w stage0_peak_detect_ word1 stage0 peak fifo word1 value 0x0f5 [15:0] x r/w stage0_max_word0 stage0 maximum value fifo word0 0x0f6 [15:0] x r/w stage0_max_word1 stage0 maximum value fifo word1 0x0f7 [15:0] x r/w stage0_max_word2 stage0 maximum value fifo word2 0x0f8 [15:0] x r/w stage0_max_word3 stage0 maximum value fifo word3 0x0f9 [15:0] x r/w stage0_max_avg stage0 average maximum fifo value 0x0fa [15:0] x r/w stage0_high_thre shold stage0 high threshold value 0x0fb [15:0] x r/w stage0_max_temp stage0 temporary maximum value 0x0fc [15:0] x r/w stage0_min_word0 stage0 minimum value fifo word0 0x0fd [15:0] x r/w stage0_min_word1 stage0 minimum value fifo word1 0x0fe [15:0] x r/w stage0_min_word2 stage0 minimum value fifo word2 0x0ff [15:0] x r/w stage0_min_word3 stage0 minimum value fifo word3 0x100 [15:0] x r/w stage0_min_avg stage0 average minimum fifo value 0x101 [15:0] x r/w stage0_low_thres hold stage0 low threshold value 0x102 [15:0] x r/w stage0_min_temp stage0 temporary minimum value 0x103 [15:0] x r/w unused set to 0
ad7147 rev. a | page 58 of 72 table 40. stage1 results registers address data bit default value type name description 0x104 [15:0] x r/w stage1_conv_data stage1 cdc 16-bit conversion data (copy of cdc_result_s1 register 0x105 [15:0] x r/w stage1_ff_word0 stage1 fast fifo word0 0x106 [15:0] x r/w stage1_ff_word1 stage1 fast fifo word1 0x107 [15:0] x r/w stage1_ff_word2 stage1 fast fifo word2 0x108 [15:0] x r/w stage1_ff_word3 stage1 fast fifo word3 0x109 [15:0] x r/w stage1_ff_word4 stage1 fast fifo word4 0x10a [15:0] x r/w stage1_ff_word5 stage1 fast fifo word5 0x10b [15:0] x r/w stage1_ff_word6 stage1 fast fifo word6 0x10c [15:0] x r/w stage1_ff_word7 stage1 fast fifo word7 0x10d [15:0] x r/w stage1_sf_word0 stage1 slow fifo word0 0x10e [15:0] x r/w stage1_sf_word1 stage1 slow fifo word1 0x10f [15:0] x r/w stage1_sf_word2 stage1 slow fifo word2 0x110 [15:0] x r/w stage1_sf_word3 stage1 slow fifo word3 0x111 [15:0] x r/w stage1_sf_word4 stage1 slow fifo word4 0x112 [15:0] x r/w stage1_sf_word5 stage1 slow fifo word5 0x113 [15:0] x r/w stage1_sf_word6 stage1 slow fifo word6 0x114 [15:0] x r/w stage1_sf_word7 stage1 slow fifo word7 0x115 [15:0] x r/w stage1_sf_ambient stage1 slow fifo ambient value 0x116 [15:0] x r/w stage1_ff_avg stage1 fast fifo average value 0x117 [15:0] x r/w stage1_peak_detect_ word0 stage1 peak fifo word0 value 0x118 [15:0] x r/w stage1_peak_detect_ word1 stage1 peak fifo word1 value 0x119 [15:0] x r/w stage1_max_word0 stage1 maximum value fifo word0 0x11a [15:0] x r/w stage1_max_word1 stage1 maximum value fifo word1 0x11b [15:0] x r/w stage1_max_word2 stage1 maximum value fifo word2 0x11c [15:0] x r/w stage1_max_word3 stage1 maximum value fifo word3 0x11d [15:0] x r/w stage1_max_avg stage1 average maximum fifo value 0x11e [15:0] x r/w stage1_high_thre shold stage1 high threshold value 0x11f [15:0] x r/w stage1_max_temp stage1 temporary maximum value 0x120 [15:0] x r/w stage1_min_word0 stage1 minimum value fifo word0 0x121 [15:0] x r/w stage1_min_word1 stage1 minimum value fifo word1 0x122 [15:0] x r/w stage1_min_word2 stage1 minimum value fifo word2 0x123 [15:0] x r/w stage1_min_word3 stage1 minimum value fifo word3 0x124 [15:0] x r/w stage1_min_avg stage1 average minimum fifo value 0x125 [15:0] x r/w stage1_low_thres hold stage1 low threshold value 0x126 [15:0] x r/w stage1_min_temp stage1 temporary minimum value 0x127 [15:0] x r/w unused set to 0
ad7147 rev. a | page 59 of 72 table 41. stage2 results registers address data bit default value type name description 0x128 [15:0] x r/w stage2_conv_data stage2 cdc 16-bit conversion data (copy of cdc_result_s2 register) 0x129 [15:0] x r/w stage2_ff_word0 stage2 fast fifo word0 0x12a [15:0] x r/w stage2_ff_word1 stage2 fast fifo word1 0x12b [15:0] x r/w stage2_ff_word2 stage2 fast fifo word2 0x12c [15:0] x r/w stage2_ff_word3 stage2 fast fifo word3 0x12d [15:0] x r/w stage2_ff_word4 stage2 fast fifo word4 0x12e [15:0] x r/w stage2_ff_word5 stage2 fast fifo word5 0x12f [15:0] x r/w stage2_ff_word6 stage2 fast fifo word6 0x130 [15:0] x r/w stage2_ff_word7 stage2 fast fifo word7 0x131 [15:0] x r/w stage2_sf_word0 stage2 slow fifo word0 0x132 [15:0] x r/w stage2_sf_word1 stage2 slow fifo word1 0x133 [15:0] x r/w stage2_sf_word2 stage2 slow fifo word2 0x134 [15:0] x r/w stage2_sf_word3 stage2 slow fifo word3 0x135 [15:0] x r/w stage2_sf_word4 stage2 slow fifo word4 0x136 [15:0] x r/w stage2_sf_word5 stage2 slow fifo word5 0x137 [15:0] x r/w stage2_sf_word6 stage2 slow fifo word6 0x138 [15:0] x r/w stage2_sf_word7 stage2 slow fifo word7 0x139 [15:0] x r/w stage2_sf_ambient stage2 slow fifo ambient value 0x13a [15:0] x r/w stage2_ff_avg stage2 fast fifo average value 0x13b [15:0] x r/w stage2_peak_detect_ word0 stage2 peak fifo word0 value 0x13c [15:0] x r/w stage2_peak_detect_ word1 stage2 peak fifo word1 value 0x13d [15:0] x r/w stage2_max_word0 stage2 maximum value fifo word0 0x13e [15:0] x r/w stage2_max_word1 stage2 maximum value fifo word1 0x13f [15:0] x r/w stage2_max_word2 stage2 maximum value fifo word2 0x140 [15:0] x r/w stage2_max_word3 stage2 maximum value fifo word3 0x141 [15:0] x r/w stage2_max_avg stage2 average maximum fifo value 0x142 [15:0] x r/w stage2_high_threshold stage2 high threshold value 0x143 [15:0] x r/w stage2_max_temp stage2 temporary maximum value 0x144 [15:0] x r/w stage2_min_word0 stage2 minimum value fifo word0 0x145 [15:0] x r/w stage2_min_word1 stage2 minimum value fifo word1 0x146 [15:0] x r/w stage2_min_word2 stage2 minimum value fifo word2 0x147 [15:0] x r/w stage2_min_word3 stage2 minimum value fifo word3 0x148 [15:0] x r/w stage2_min_avg stage2 average minimum fifo value 0x149 [15:0] x r/w stage2_low_thres hold stage2 low threshold value 0x14a [15:0] x r/w stage2_min_temp stage2 temporary minimum value 0x14b [15:0] x r/w unused set to 0
ad7147 rev. a | page 60 of 72 table 42. stage3 results registers address data bit default value type name description 0x14c [15:0] x r/w stage3_conv_data stage3 cdc 16-bit conversion data (copy of cdc_result_s3 register) 0x14d [15:0] x r/w stage3_ff_word0 stage3 fast fifo word0 0x14e [15:0] x r/w stage3_ff_word1 stage3 fast fifo word1 0x14f [15:0] x r/w stage3_ff_word2 stage3 fast fifo word2 0x150 [15:0] x r/w stage3_ff_word3 stage3 fast fifo word3 0x151 [15:0] x r/w stage3_ff_word4 stage3 fast fifo word4 0x152 [15:0] x r/w stage3_ff_word5 stage3 fast fifo word5 0x153 [15:0] x r/w stage3_ff_word6 stage3 fast fifo word6 0x154 [15:0] x r/w stage3_ff_word7 stage3 fast fifo word7 0x155 [15:0] x r/w stage3_sf_word0 stage3 slow fifo word0 0x156 [15:0] x r/w stage3_sf_word1 stage3 slow fifo word1 0x157 [15:0] x r/w stage3_sf_word2 stage3 slow fifo word2 0x158 [15:0] x r/w stage3_sf_word3 stage3 slow fifo word3 0x159 [15:0] x r/w stage3_sf_word4 stage3 slow fifo word4 0x15a [15:0] x r/w stage3_sf_word5 stage3 slow fifo word5 0x15b [15:0] x r/w stage3_sf_word6 stage3 slow fifo word6 0x15c [15:0] x r/w stage3_sf_word7 stage3 slow fifo word7 0x15d [15:0] x r/w stage3_sf_ambient stage3 slow fifo ambient value 0x15e [15:0] x r/w stage3_ff_avg stage3 fast fifo average value 0x15f [15:0] x r/w stage3_peak_detect_ word0 stage3 peak fifo word0 value 0x160 [15:0] x r/w stage3_peak_detect_ word1 stage3 peak fifo word1 value 0x161 [15:0] x r/w stage3_max_word0 stage3 maximum value fifo word0 0x162 [15:0] x r/w stage3_max_word1 stage3 maximum value fifo word1 0x163 [15:0] x r/w stage3_max_word2 stage3 maximum value fifo word2 0x164 [15:0] x r/w stage3_max_word3 stage3 maximum value fifo word3 0x165 [15:0] x r/w stage3_max_avg stage3 average maximum fifo value 0x166 [15:0] x r/w stage3_high_threshold stage3 high threshold value 0x167 [15:0] x r/w stage3_max_temp stage3 temporary maximum value 0x168 [15:0] x r/w stage3_min_word0 stage3 minimum value fifo word0 0x169 [15:0] x r/w stage3_min_word1 stage3 minimum value fifo word1 0x16a [15:0] x r/w stage3_min_word2 stage3 minimum value fifo word2 0x16b [15:0] x r/w stage3_min_word3 stage3 minimum value fifo word3 0x16c [15:0] x r/w stage3_min_avg stage3 average minimum fifo value 0x16d [15:0] x r/w stage3_low_thr eshold stage3 low threshold value 0x16e [15:0] x r/w stage3_min_temp stage3 temporary minimum value 0x16f [15:0] x r/w unused set to 0
ad7147 rev. a | page 61 of 72 table 43. stage4 results registers address data bit default value type name description 0x170 [15:0] x r/w stage4_conv_data stage4 cdc 16-bit conversion data (copy of cdc_result_s4 register) 0x171 [15:0] x r/w stage4_ff_word0 stage4 fast fifo word0 0x172 [15:0] x r/w stage4_ff_word1 stage4 fast fifo word1 0x173 [15:0] x r/w stage4_ff_word2 stage4 fast fifo word2 0x174 [15:0] x r/w stage4_ff_word3 stage4 fast fifo word3 0x175 [15:0] x r/w stage4_ff_word4 stage4 fast fifo word4 0x176 [15:0] x r/w stage4_ff_word5 stage4 fast fifo word5 0x177 [15:0] x r/w stage4_ff_word6 stage4 fast fifo word6 0x178 [15:0] x r/w stage4_ff_word7 stage4 fast fifo word7 0x179 [15:0] x r/w stage4_sf_word0 stage4 slow fifo word0 0x17a [15:0] x r/w stage4_sf_word1 stage4 slow fifo word1 0x17b [15:0] x r/w stage4_sf_word2 stage4 slow fifo word2 0x17c [15:0] x r/w stage4_sf_word3 stage4 slow fifo word3 0x17d [15:0] x r/w stage4_sf_word4 stage4 slow fifo word4 0x17e [15:0] x r/w stage4_sf_word5 stage4 slow fifo word5 0x17f [15:0] x r/w stage4_sf_word6 stage4 slow fifo word6 0x180 [15:0] x r/w stage4_sf_word7 stage4 slow fifo word7 0x181 [15:0] x r/w stage4_sf_ambient stage4 slow fifo ambient value 0x182 [15:0] x r/w stage4_ff_avg stage4 fast fifo average value 0x183 [15:0] x r/w stage4_peak_detect_ word0 stage4 peak fifo word0 value 0x184 [15:0] x r/w stage4_peak_detect_ word1 stage4 peak fifo word1 value 0x185 [15:0] x r/w stage4_max_word0 stage4 maximum value fifo word0 0x186 [15:0] x r/w stage4_max_word1 stage4 maximum value fifo word1 0x187 [15:0] x r/w stage4_max_word2 stage4 maximum value fifo word2 0x188 [15:0] x r/w stage4_max_word3 stage4 maximum value fifo word3 0x189 [15:0] x r/w stage4_max_avg stage4 average maximum fifo value 0x18a [15:0] x r/w stage4_high_thre shold stage4 high threshold value 0x18b [15:0] x r/w stage4_max_temp stage4 temporary maximum value 0x18c [15:0] x r/w stage4_min_word0 stage4 minimum value fifo word0 0x18d [15:0] x r/w stage4_min_word1 stage4 minimum value fifo word1 0x18e [15:0] x r/w stage4_min_word2 stage4 minimum value fifo word2 0x18f [15:0] x r/w stage4_min_word3 stage4 minimum value fifo word3 0x190 [15:0] x r/w stage4_min_avg stage4 average minimum fifo value 0x191 [15:0] x r/w stage4_low_thres hold stage4 low threshold value 0x192 [15:0] x r/w stage4_min_temp stage4 temporary minimum value 0x193 [15:0] x r/w unused set to 0
ad7147 rev. a | page 62 of 72 table 44. stage5 results registers address data bit default value type name description 0x194 [15:0] x r/w stage5_conv_data stage5 cdc 16-bit conversion data (copy of cdc_result_s5 register) 0x195 [15:0] x r/w stage5_ff_word0 stage5 fast fifo word0 0x196 [15:0] x r/w stage5_ff_word1 stage5 fast fifo word1 0x197 [15:0] x r/w stage5_ff_word2 stage5 fast fifo word2 0x198 [15:0] x r/w stage5_ff_word3 stage5 fast fifo word3 0x199 [15:0] x r/w stage5_ff_word4 stage5 fast fifo word4 0x19a [15:0] x r/w stage5_ff_word5 stage5 fast fifo word5 0x19b [15:0] x r/w stage5_ff_word6 stage5 fast fifo word6 0x19c [15:0] x r/w stage5_ff_word7 stage5 fast fifo word7 0x19d [15:0] x r/w stage5_sf_word0 stage5 slow fifo word0 0x19e [15:0] x r/w stage5_sf_word1 stage5 slow fifo word1 0x19f [15:0] x r/w stage5_sf_word2 stage5 slow fifo word2 0x1a0 [15:0] x r/w stage5_sf_word3 stage5 slow fifo word3 0x1a1 [15:0] x r/w stage5_sf_word4 stage5 slow fifo word4 0x1a2 [15:0] x r/w stage5_sf_word5 stage5 slow fifo word5 0x1a3 [15:0] x r/w stage5_sf_word6 stage5 slow fifo word6 0x1a4 [15:0] x r/w stage5_sf_word7 stage5 slow fifo word7 0x1a5 [15:0] x r/w stage5_sf_ambient stage5 slow fifo ambient value 0x1a6 [15:0] x r/w stage5_ff_avg stage5 fast fifo average value 0x1a7 [15:0] x r/w stage5_peak_detect_ word0 stage5 peak fifo word0 value 0x1a8 [15:0] x r/w stage5_peak_detect_ word1 stage5 peak fifo word1 value 0x1a9 [15:0] x r/w stage5_max_word0 stage5 maximum value fifo word0 0x1aa [15:0] x r/w stage5_max_word1 stage5 maximum value fifo word1 0x1ab [15:0] x r/w stage5_max_word2 stage5 maximum value fifo word2 0x1ac [15:0] x r/w stage5_max_word3 stage5 maximum value fifo word3 0x1ad [15:0] x r/w stage5_max_avg stage5 average maximum fifo value 0x1ae [15:0] x r/w stage5_high_thre shold stage5 high threshold value 0x1af [15:0] x r/w stage5_max_temp stage5 temporary maximum value 0x1b0 [15:0] x r/w stage5_min_word0 stage5 minimum value fifo word0 0x1b1 [15:0] x r/w stage5_min_word1 stage5 minimum value fifo word1 0x1b2 [15:0] x r/w stage5_min_word2 stage5 minimum value fifo word2 0x1b3 [15:0] x r/w stage5_min_word3 stage5 minimum value fifo word3 0x1b4 [15:0] x r/w stage5_min_avg stage5 average minimum fifo value 0x1b5 [15:0] x r/w stage5_low_thr eshold stage5 low threshold value 0x1b6 [15:0] x r/w stage5_min_temp stage5 temporary minimum value 0x1b7 [15:0] x r/w unused set to 0
ad7147 rev. a | page 63 of 72 table 45. stage6 results registers address data bit default value type name description 0x1b8 [15:0] x r/w stage6_conv_data stage6 cdc 16-bit conversion data (copy of cdc_result_s6 register) 0x1b9 [15:0] x r/w stage6_ff_word0 stage6 fast fifo word0 0x1ba [15:0] x r/w stage6_ff_word1 stage6 fast fifo word1 0x1bb [15:0] x r/w stage6_ff_word2 stage6 fast fifo word2 0x1bc [15:0] x r/w stage6_ff_word3 stage6 fast fifo word3 0x1bd [15:0] x r/w stage6_ff_word4 stage6 fast fifo word4 0x1be [15:0] x r/w stage6_ff_word5 stage6 fast fifo word5 0x1bf [15:0] x r/w stage6_ff_word6 stage6 fast fifo word6 0x1c0 [15:0] x r/w stage6_ff_word7 stage6 fast fifo word7 0x1c1 [15:0] x r/w stage6_sf_word0 stage6 slow fifo word0 0x1c2 [15:0] x r/w stage6_sf_word1 stage6 slow fifo word1 0x1c3 [15:0] x r/w stage6_sf_word2 stage6 slow fifo word2 0x1c4 [15:0] x r/w stage6_sf_word3 stage6 slow fifo word3 0x1c5 [15:0] x r/w stage6_sf_word4 stage6 slow fifo word4 0x1c6 [15:0] x r/w stage6_sf_word5 stage6 slow fifo word5 0x1c7 [15:0] x r/w stage6_sf_word6 stage6 slow fifo word6 0x1c8 [15:0] x r/w stage6_sf_word7 stage6 slow fifo word7 0x1c9 [15:0] x r/w stage6_sf_ambient stage6 slow fifo ambient value 0x1ca [15:0] x r/w stage6_ff_avg stage6 fast fifo average value 0x1cb [15:0] x r/w stage6_peak_detect_ word0 stage6 peak fifo word0 value 0x1cc [15:0] x r/w stage6_peak_detect_ word1 stage6 peak fifo word1 value 0x1cd [15:0] x r/w stage6_max_word0 stage6 maximum value fifo word0 0x1ce [15:0] x r/w stage6_max_word1 stage6 maximum value fifo word1 0x1cf [15:0] x r/w stage6_max_word2 stage6 maximum value fifo word2 0x1d0 [15:0] x r/w stage6_max_word3 stage6 maximum value fifo word3 0x1d1 [15:0] x r/w stage6_max_avg stage6 average maximum fifo value 0x1d2 [15:0] x r/w stage6_high_threshold stage6 high threshold value 0x1d3 [15:0] x r/w stage6_max_temp stage6 temporary maximum value 0x1d4 [15:0] x r/w stage6_min_word0 stage6 minimum value fifo word0 0x1d5 [15:0] x r/w stage6_min_word1 stage6 minimum value fifo word1 0x1d6 [15:0] x r/w stage6_min_word2 stage6 minimum value fifo word2 0x1d7 [15:0] x r/w stage6_min_word3 stage6 minimum value fifo word3 0x1d8 [15:0] x r/w stage6_min_avg stage6 average minimum fifo value 0x1d9 [15:0] x r/w stage6_low_thr eshold stage6 low threshold value 0x1da [15:0] x r/w stage6_min_temp stage6 temporary minimum value 0x1db [15:0] x r/w unused set to 0
ad7147 rev. a | page 64 of 72 table 46. stage7 results registers address data bit default value type name description 0x1dc [15:0] x r/w stage7_conv_data stage7 cdc 16-bit conversion data (copy of cdc_result_s7 register) 0x1dd [15:0] x r/w stage7_ff_word0 stage7 fast fifo word0 0x1de [15:0] x r/w stage7_ff_word1 stage7 fast fifo word1 0x1df [15:0] x r/w stage7_ff_word2 stage7 fast fifo word2 0x1e0 [15:0] x r/w stage7_ff_word3 stage7 fast fifo word3 0x1e1 [15:0] x r/w stage7_ff_word4 stage7 fast fifo word4 0x1e2 [15:0] x r/w stage7_ff_word5 stage7 fast fifo word5 0x1e3 [15:0] x r/w stage7_ff_word6 stage7 fast fifo word6 0x1e4 [15:0] x r/w stage7_ff_word7 stage7 fast fifo word7 0x1e5 [15:0] x r/w stage7_sf_word0 stage7 slow fifo word0 0x1e6 [15:0] x r/w stage7_sf_word1 stage7 slow fifo word1 0x1e7 [15:0] x r/w stage7_sf_word2 stage7 slow fifo word2 0x1e8 [15:0] x r/w stage7_sf_word3 stage7 slow fifo word3 0x1e9 [15:0] x r/w stage7_sf_word4 stage7 slow fifo word4 0x1ea [15:0] x r/w stage7_sf_word5 stage7 slow fifo word5 0x1eb [15:0] x r/w stage7_sf_word6 stage7 slow fifo word6 0x1ec [15:0] x r/w stage7_sf_word7 stage7 slow fifo word7 0x1ed [15:0] x r/w stage7_sf_ambient stage7 slow fifo ambient value 0x1ee [15:0] x r/w stage7_ff_avg stage7 fast fifo average value 0x1ef [15:0] x r/w stage7_peak_detect_ word0 stage7 peak fifo word0 value 0x1f0 [15:0] x r/w stage7_peak_detect_ word1 stage7 peak fifo word1 value 0x1f1 [15:0] x r/w stage7_max_word0 stage7 maximum value fifo word0 0x1f2 [15:0] x r/w stage7_max_word1 stage7 maximum value fifo word1 0x1f3 [15:0] x r/w stage7_max_word2 stage7 maximum value fifo word2 0x1f4 [15:0] x r/w stage7_max_word3 stage7 maximum value fifo word3 0x1f5 [15:0] x r/w stage7_max_avg stage7 average maximum fifo value 0x1f6 [15:0] x r/w stage7_high_threshold stage7 high threshold value 0x1f7 [15:0] x r/w stage7_max_temp stage7 temporary maximum value 0x1f8 [15:0] x r/w stage7_min_word0 stage7 minimum value fifo word0 0x1f9 [15:0] x r/w stage7_min_word1 stage7 minimum value fifo word1 0x1fa [15:0] x r/w stage7_min_word2 stage7 minimum value fifo word2 0x1fb [15:0] x r/w stage7_min_word3 stage7 minimum value fifo word3 0x1fc [15:0] x r/w stage7_min_avg stage7 average minimum fifo value 0x1fd [15:0] x r/w stage7_low_thr eshold stage7 low threshold value 0x1fe [15:0] x r/w stage7_min_temp stage7 temporary minimum value 0x1ff [15:0] x r/w unused set to 0
ad7147 rev. a | page 65 of 72 table 47. stage8 results registers address data bit default value type name description 0x200 [15:0] x r/w stage8_conv_data stage8 cdc 16-bit conversion data (copy of cdc_result_s8 register) 0x201 [15:0] x r/w stage8_ff_word0 stage8 fast fifo word0 0x202 [15:0] x r/w stage8_ff_word1 stage8 fast fifo word1 0x203 [15:0] x r/w stage8_ff_word2 stage8 fast fifo word2 0x204 [15:0] x r/w stage8_ff_word3 stage8 fast fifo word3 0x205 [15:0] x r/w stage8_ff_word4 stage8 fast fifo word4 0x206 [15:0] x r/w stage8_ff_word5 stage8 fast fifo word5 0x207 [15:0] x r/w stage8_ff_word6 stage8 fast fifo word6 0x208 [15:0] x r/w stage8_ff_word7 stage8 fast fifo word7 0x209 [15:0] x r/w stage8_sf_word0 stage8 slow fifo word0 0x20a [15:0] x r/w stage8_sf_word1 stage8 slow fifo word1 0x20b [15:0] x r/w stage8_sf_word2 stage8 slow fifo word2 0x20c [15:0] x r/w stage8_sf_word3 stage8 slow fifo word3 0x20d [15:0] x r/w stage8_sf_word4 stage8 slow fifo word4 0x20e [15:0] x r/w stage8_sf_word5 stage8 slow fifo word5 0x20f [15:0] x r/w stage8_sf_word6 stage8 slow fifo word6 0x210 [15:0] x r/w stage8_sf_word7 stage8 slow fifo word7 0x211 [15:0] x r/w stage8_sf_ambient stage8 slow fifo ambient value 0x212 [15:0] x r/w stage8_ff_avg stage8 fast fifo average value 0x213 [15:0] x r/w stage8_peak_detect_ word0 stage8 peak fifo word0 value 0x214 [15:0] x r/w stage8_peak_detect_ word1 stage8 peak fifo word1 value 0x215 [15:0] x r/w stage8_max_word0 stage8 maximum value fifo word0 0x216 [15:0] x r/w stage8_max_word1 stage8 maximum value fifo word1 0x217 [15:0] x r/w stage8_max_word2 stage8 maximum value fifo word2 0x218 [15:0] x r/w stage8_max_word3 stage8 maximum value fifo word3 0x219 [15:0] x r/w stage8_max_avg stage8 average maximum fifo value 0x21a [15:0] x r/w stage8_high_thre shold stage8 high threshold value 0x21b [15:0] x r/w stage8_max_temp stage8 temporary maximum value 0x21c [15:0] x r/w stage8_min_word0 stage8 minimum value fifo word0 0x21d [15:0] x r/w stage8_min_word1 stage8 minimum value fifo word1 0x21e [15:0] x r/w stage8_min_word2 stage8 minimum value fifo word2 0x21f [15:0] x r/w stage8_min_word3 stage8 minimum value fifo word3 0x220 [15:0] x r/w stage8_min_avg stage8 average minimum fifo value 0x221 [15:0] x r/w stage8_low_thres hold stage8 low threshold value 0x222 [15:0] x r/w stage8_min_temp stage7 temporary minimum value 0x223 [15:0] x r/w unused set to 0
ad7147 rev. a | page 66 of 72 table 48. stage9 results registers address data bit default value type name description 0x224 [15:0] x r/w stage9_conv_data stage9 cdc 16-bit conversion data (copy of cdc_result_s9 register) 0x225 [15:0] x r/w stage9_ff_word0 stage9 fast fifo word0 0x226 [15:0] x r/w stage9_ff_word1 stage9 fast fifo word1 0x227 [15:0] x r/w stage9_ff_word2 stage9 fast fifo word2 0x228 [15:0] x r/w stage9_ff_word3 stage9 fast fifo word3 0x229 [15:0] x r/w stage9_ff_word4 stage9 fast fifo word4 0x22a [15:0] x r/w stage9_ff_word5 stage9 fast fifo word5 0x22b [15:0] x r/w stage9_ff_word6 stage9 fast fifo word6 0x22c [15:0] x r/w stage9_ff_word7 stage9 fast fifo word7 0x22d [15:0] x r/w stage9_sf_word0 stage9 slow fifo word0 0x22e [15:0] x r/w stage9_sf_word1 stage9 slow fifo word1 0x22f [15:0] x r/w stage9_sf_word2 stage9 slow fifo word2 0x230 [15:0] x r/w stage9_sf_word3 stage9 slow fifo word3 0x231 [15:0] x r/w stage9_sf_word4 stage9 slow fifo word4 0x232 [15:0] x r/w stage9_sf_word5 stage9 slow fifo word5 0x233 [15:0] x r/w stage9_sf_word6 stage9 slow fifo word6 0x234 [15:0] x r/w stage9_sf_word7 stage9 slow fifo word7 0x235 [15:0] x r/w stage9_sf_ambient stage9 slow fifo ambient value 0x236 [15:0] x r/w stage9_ff_avg stage9 fast fifo average value 0x237 [15:0] x r/w stage9_peak_detect_ word0 stage9 peak fifo word0 value 0x238 [15:0] x r/w stage9_peak_detect_ word1 stage9 peak fifo word1 value 0x239 [15:0] x r/w stage9_max_word0 stage9 maximum value fifo word0 0x23a [15:0] x r/w stage9_max_word1 stage9 maximum value fifo word1 0x23b [15:0] x r/w stage9_max_word2 stage9 maximum value fifo word2 0x23c [15:0] x r/w stage9_max_word3 stage9 maximum value fifo word3 0x23d [15:0] x r/w stage9_max_avg stage9 average maximum fifo value 0x23e [15:0] x r/w stage9_high_thre shold stage9 high threshold value 0x23f [15:0] x r/w stage9_max_temp stage9 temporary maximum value 0x240 [15:0] x r/w stage9_min_word0 stage9 minimum value fifo word0 0x241 [15:0] x r/w stage9_min_word1 stage9 minimum value fifo word1 0x242 [15:0] x r/w stage9_min_word2 stage9 minimum value fifo word2 0x243 [15:0] x r/w stage9_min_word3 stage9 minimum value fifo word3 0x244 [15:0] x r/w stage9_min_avg stage9 average minimum fifo value 0x245 [15:0] x r/w stage9_low_thres hold stage9 low threshold value 0x246 [15:0] x r/w stage9_min_temp stage9 temporary minimum value 0x247 [15:0] x r/w unused set to 0
ad7147 rev. a | page 67 of 72 table 49. stage10 results registers address data bit default value type name description 0x248 [15:0] x r/w stage10_conv_data stage10 cdc 16-bit conversion data (copy of cdc_result_s10 register) 0x249 [15:0] x r/w stage10_ff_word0 stage10 fast fifo word0 0x24a [15:0] x r/w stage10_ff_word1 stage10 fast fifo word1 0x24b [15:0] x r/w stage10_ff_word2 stage10 fast fifo word2 0x24c [15:0] x r/w stage10_ff_word3 stage10 fast fifo word3 0x24d [15:0] x r/w stage10_ff_word4 stage10 fast fifo word4 0x24e [15:0] x r/w stage10_ff_word5 stage10 fast fifo word5 0x24f [15:0] x r/w stage10_ff_word6 stage10 fast fifo word6 0x250 [15:0] x r/w stage10_ff_word7 stage10 fast fifo word7 0x251 [15:0] x r/w stage10_sf_word0 stage10 slow fifo word0 0x252 [15:0] x r/w stage10_sf_word1 stage10 slow fifo word1 0x253 [15:0] x r/w stage10_sf_word2 stage10 slow fifo word2 0x254 [15:0] x r/w stage10_sf_word3 stage10 slow fifo word3 0x255 [15:0] x r/w stage10_sf_word4 stage10 slow fifo word4 0x256 [15:0] x r/w stage10_sf_word5 stage10 slow fifo word5 0x257 [15:0] x r/w stage10_sf_word6 stage10 slow fifo word6 0x258 [15:0] x r/w stage10_sf_word7 stage10 slow fifo word7 0x259 [15:0] x r/w stage10_sf_ambient stage10 slow fifo ambient value 0x25a [15:0] x r/w stage10_ff_avg stage10 fast fifo average value 0x25b [15:0] x r/w stage10_peak_detect_word0 stage10 peak fifo word0 value 0x25c [15:0] x r/w stage10_peak_detect_word1 stage10 peak fifo word1 value 0x25d [15:0] x r/w stage10_max_word0 stage10 maximum value fifo word0 0x25e [15:0] x r/w stage10_max_word1 stage10 maximum value fifo word1 0x25f [15:0] x r/w stage10_max_word 2 stage10 maximum value fifo word2 0x260 [15:0] x r/w stage10_max_word3 stage10 maximum value fifo word3 0x261 [15:0] x r/w stage10_max_avg stage10 average maximum fifo value 0x262 [15:0] x r/w stage10_high_thres hold stage10 high threshold value 0x263 [15:0] x r/w stage10_max_temp stage10 temporary maximum value 0x264 [15:0] x r/w stage10_min_word0 stage10 minimum value fifo word0 0x265 [15:0] x r/w stage10_min_word1 stage10 minimum value fifo word1 0x266 [15:0] x r/w stage10_min_word2 stage10 minimum value fifo word2 0x267 [15:0] x r/w stage10_min_word3 stage10 minimum value fifo word3 0x268 [15:0] x r/w stage10_min_avg stage10 average minimum fifo value 0x269 [15:0] x r/w stage10_low_threshold stage10 low threshold value 0x26a [15:0] x r/w stage10_min_temp stage10 temporary minimum value 0x26b [15:0] x r/w unused set to 0
ad7147 rev. a | page 68 of 72 table 50. stage11 results registers address data bit default value type name description 0x26c [15:0] x r/w stage11_conv_data stage11 cdc 16-bit conversion data (copy of cdc_result_s11 register) 0x26d [15:0] x r/w stage11_ff_word0 stage11 fast fifo word0 0x26e [15:0] x r/w stage11_ff_word1 stage11 fast fifo word1 0x26f [15:0] x r/w stage11_ff_word2 stage11 fast fifo word2 0x270 [15:0] x r/w stage11_ff_word3 stage11 fast fifo word3 0x271 [15:0] x r/w stage11_ff_word4 stage11 fast fifo word4 0x272 [15:0] x r/w stage11_ff_word5 stage11 fast fifo word5 0x273 [15:0] x r/w stage11_ff_word6 stage11 fast fifo word6 0x274 [15:0] x r/w stage11_ff_word7 stage11 fast fifo word7 0x275 [15:0] x r/w stage11_sf_word0 stage11 slow fifo word0 0x276 [15:0] x r/w stage11_sf_word1 stage11 slow fifo word1 0x277 [15:0] x r/w stage11_sf_word2 stage11 slow fifo word2 0x278 [15:0] x r/w stage11_sf_word3 stage11 slow fifo word3 0x279 [15:0] x r/w stage11_sf_word4 stage11 slow fifo word4 0x27a [15:0] x r/w stage11_sf_word5 stage11 slow fifo word5 0x27b [15:0] x r/w stage11_sf_word6 stage11 slow fifo word6 0x27c [15:0] x r/w stage11_sf_word7 stage11 slow fifo word7 0x27d [15:0] x r/w stage11_sf_ambient stage11 slow fifo ambient value 0x27e [15:0] x r/w stage11_ff_avg stage11 fast fifo average value 0x27f [15:0] x r/w stage11_peak_detect_ word0 stage11 peak fifo word0 value 0x280 [15:0] x r/w stage11_peak_detect_word1 stage11 peak fifo word1 value 0x281 [15:0] x r/w stage11_max_word0 stage11 maximum value fifo word0 0x282 [15:0] x r/w stage11_max_word1 stage11 maximum value fifo word1 0x283 [15:0] x r/w stage11_max_word2 stage11 maximum value fifo word2 0x284 [15:0] x r/w stage11_max_word3 stage11 maximum value fifo word3 0x285 [15:0] x r/w stage11_max_avg stage11 average maximum fifo value 0x286 [15:0] x r/w stage11_high_thres hold stage11 high threshold value 0x287 [15:0] x r/w stage11_max_temp stage11 temporary maximum value 0x288 [15:0] x r/w stage11_min_word0 stage11 minimum value fifo word0 0x289 [15:0] x r/w stage11_min_word1 stage11 minimum value fifo word1 0x28a [15:0] x r/w stage11_min_word2 stage11 minimum value fifo word2 0x28b [15:0] x r/w stage11_min_word3 stage11 minimum value fifo word3 0x28c [15:0] x r/w stage11_min_avg stage11 average minimum fifo value 0x28d [15:0] x r/w stage11_low_threshold stage11 low threshold value 0x28e [15:0] x r/w stage11_min_temp stage11 temporary minimum value 0x28f [15:0] x r/w unused set to 0
ad7147 rev. a | page 69 of 72 outline dimensions compliant to jedec standards mo-220-vggd-8 1 24 6 7 13 19 18 12 2.65 2.50 sq 2.35 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.23 min *exposed pa d (bottom view) * note: the exposed pad is not connected internally. for increased reliability of the solder joints and maximum thermal capability it is recommended that the pad be soldered to the ground plane. 011708-a figure 63. 24-lead frame chip scale package [lfcsp_vq] 4 mm 4 mm very thin quad (cp-24-3) dimensions shown in millimeters ordering guide model temperature range description serial interface description package description package option ad7147acpz-reel 1 C40c to +85c wake up on touch spi interface 24-lead lfcsp_vq cp-24-3 ad7147acpz-500rl7 1 C40c to +85c wake up on touch spi interface 24-lead lfcsp_vq cp-24-3 ad7147pacpz-rl 1 C40c to +85c wake up on proximity spi interface 24-lead lfcsp_vq cp-24-3 ad7147pacpz-500r7 1 C40c to +85c wake up on proximity spi interface 24-lead lfcsp_vq cp-24-3 ad7147acpz-1reel 1 C40c to +85c wake up on touch i 2 c interface 24-lead lfcsp_vq cp-24-3 AD7147ACPZ-1500RL7 1 C40c to +85c wake up on touch i 2 c interface 24-lead lfcsp_vq cp-24-3 ad7147pacpz-1rl 1 C40c to +85c wake up on proximity i 2 c interface 24-lead lfcsp_vq cp-24-3 ad7147pacpz-1500r7 1 C40c to +85c wake up on proximity i 2 c interface 24-lead lfcsp_vq cp-24-3 eval-ad7147ebz 1 spi interface evaluation board eval-ad7147-1ebz 1 i 2 c interface evaluation board 1 z = rohs compliant part.
ad7147 rev. a | page 70 of 72 notes
ad7147 rev. a | page 71 of 72 notes
ad7147 rev. a | page 72 of 72 notes ?2007C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06663-0-8/08(a)

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